Design for Test Engineer

Apple Inc.; Austin, Northern (TX, KY); Hybrid; USD 140,000 - 190,000; Full time

Job summary

Apple Inc. in Austin, Texas is seeking a DFT/ATPG design engineer to lead scan insertion and ATPG during the DFT design phase. You will work with DV, Front-End, PD and STA teams to resolve hardware design issues and deliver configurations for RTL generation.

You will also create infrastructure to improve design cycles and maintain high-quality pattern generation and coverage. The role requires a Master’s in Electrical/Electronics Engineering and 2 years of related experience, with strong Verilog

Qualifications

• Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field.
• 2 years of experience in the job offered or related occupation.
• Experience with Verilog RTL for DFT IP.
• Experience with RTL design for DFT features (scan codec, ATPG isolation, scan routing).
• Experience with scripting languages (Python, Perl, TCL) including automation of design flows, verification, synthesis and modeling.
• Experience with basic FE tools (CDC, RDC, Lint) and understanding of clock/reset domains.
• Experience with synthesis tools and configuring constraints for synthesis.
• Experience with ATPG tools for Scan DRC and ATPG coverage.
• Knowledge of computer architecture principles and SOC development flows for DFT analysis.
• Knowledge of Scan and MBIST DFT architecture and implementation concepts.

Responsibilities

• Lead scan insertion and ATPG during DFT design development.
• Deliver configs and scripts for RTL generation and scans.
• Debug and support Front-end team to ensure high-quality scan insertion.
• Support PD, STA and DV teams on scan-related issues.
• Improve ATPG flows to achieve higher stuck-at coverage.
• Collaborate with CAD team and tool vendors to resolve issues and improve flows.
• Debug simulations and silicon failures; implement RTL/script/config changes.
• Create infrastructure to improve design cycle and add new checks for RTL issues.
• Ensure compliance with specs across STA, physical, power and logic areas.

Skills

Verilog RTL for DFT

RTL Design for DFT

Scripting: Python/Perl/TCL

FE tools: CDC RDC Lint

Synthesis constraints/configs

ATPG for Scan DRC

ATPG coverage analysis

Computer architecture basics

Scan/MBIST DFT concepts

Education

Master's degree in Electrical/Electronics Engineering

Job description

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Austin, Texas. Responsible for scan insertion and ATPG (Automatic Pattern Generation) during the DFT design development phase which involves collaborating with different cross functional teams (DV, Front-End, PD and STA team) on solving hardware design issues. Deliver collaterals (configs and scripts) which are used by the Front-end team during RTL generation for scan insertion. Debug and provide support to Front-end team to tackle challenges and ensure high quality of scan insertion in the design during synthesis. Support the PD, STA and DV team on issues faced due to scan insertion. Ensure high quality of pattern generation and achieve higher stuck-at coverage, using ATPG tool, by maintaining and improving ATPG flows. Work with CAD team and tool vendor to resolve issues and improve flows. Debug simulation and silicon failures and solve issues through RTL, script, or configuration changes. Generate patterns at partition-level and top-level and make sure that they achieve targeted coverage according to project specifications. Create infrastructure to improve the design cycle and to implement new checks to catch more RTL issues early in the design cycle. Meet the deadlines of projects and deliver high quality results. Implement DFT infrastructure to maintain high quality results while working with the DV team to verify DFT implementations and implement ECOs. Ensure compliance with specifications and codes by working with designers on STA, physical, power and logical issues. 40 hours/week.

Minimum Qualifications

• Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field and 2 years of experience in the job offered or related occupation.
• Experience and/or education must include:
• Utilizing Verilog to write RTL for DFT IP
• Utilizing RTL Design for DFT features such as scan codec, ATPG isolation, and scan routing
• Utilizing Scripting language (Python, Perl, or TCL) including automation of design flows, verification, synthesis and modeling
• Utilizing basic FE tools (CDC, RDC, Lint) with understanding of clock and reset domain and error resolution
• Utilizing synthesis tools and setting up of constraints and configurations for synthesis
• Utilizing ATPG tools for Scan DRC (w/error resolution) and ATPG coverage (w/analysis and improvement)
• Utilizing computer architecture principles and basic SOC development flows to allow for productive DFT analysis and debug
• Utilizing Scan and MBIST DFT architecture and implementation concepts to enable effective DFT implementation

Preferred Qualifications

• N/A

This position is not subject to the application limits.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

At Apple, we believe accessibility is a fundamental human right. You'll find that idea reflected in everything here - in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple's workplace

Learn about reasonable accommodations for job applicants

Apple accepts applications to this posting on an ongoing basis.