DFT & ATPG Design Engineer for CPU Cores & Cache

AMD; Fort Collins (CO); On-site; USD 120,000 - 150,000; Full time

Job summary

AMD is seeking a DFT/ATPG Design and Test Engineer to support the development and manufacturing readiness of next-generation CPU cores and caches.

You will own scan test pattern delivery, improve scan architecture, and partner with design, physical design, and product test teams to solve complex technical challenges and improve product quality. This role emphasizes cross-functional collaboration and advanced DFT methods to enable high-frequency CPU designs.

Qualifications

• Experience with design-for-test methodologies, especially scan testing and ATPG.
• Strong knowledge of ATPG tools and applying them to pattern generation and fault coverage.
• Experience debugging ATPG patterns, scan structures, test models, and gate-level netlists.
• Understanding IEEE 1149.1 boundary scan, IEEE 1500 embedded core test, and memory built-in self-test concepts.
• Experience with multi-clock and multi-power-domain designs.
• Familiarity with static timing analysis, clock-domain crossing analysis, static power analysis, and physical design closure.
• Experience adapting standard DFT tools or methods to meet performance requirements of complex designs.
• CPU or cache architecture experience is preferred; strong DFT candidates from related ASIC environments may also be considered.

Responsibilities

• Own the generation, validation, and delivery of scan test patterns for next-generation CPU cores and caches.
• Partner with product test teams during test bring-up and troubleshoot pattern, model, and netlist issues.
• Improve scan architecture, scan coverage, test models, execution methods, and overall product quality.
• Perform ATPG pattern and gate-level netlist analysis to identify and resolve testability and coverage issues.
• Collaborate with physical design engineers to support design closure through static timing, clock-domain crossing, netlist, and power analysis.
• Address DFT requirements for high-frequency CPU designs while minimizing performance impact.
• Resolve complex interactions between intellectual property and system-on-chip design environments across global teams.
• Develop and implement improvements that simplify design complexity and strengthen engineering quality.
• Contribute to the continued evolution of CPU cache array and DFT design practices.

Skills

DFT/ATPG

Scan test

ATPG tools

Pattern debugging

Gate-level nets

IEEE boundary scan

Clock-domain crossing

Static timing analysis

Power analysis

Team collaboration

Education

Bachelor/Master in Electrical or Computer Engineering

Tools

Boundary scan tools

ATPG tools

Power/Timing analysis tools

Job description

AMD is seeking a DFT/ATPG Design and Test Engineer to support the development and manufacturing readiness of next-generation CPU cores and caches.

You will own scan test pattern delivery, improve scan architecture, and partner with design, physical design, and product test teams to solve complex technical challenges and improve product quality. This role emphasizes cross-functional collaboration and advanced DFT methods to enable high-frequency CPU designs.