DFT ATPG Design and Test Engineer - AMD

OpenTalent; Fort Collins (CO); On-site; USD 110,000 - 170,000; Full time

Job summary

AMD is seeking a DFT/ATPG Design and Test Engineer to support the development and manufacturing readiness of next-generation CPU cores and caches in its Cores Organization. You will own scan test pattern delivery, support test bring-up, and collaborate with design, physical design, and product test teams to improve coverage and quality.

You will analyze gate-level nets, enhance scan architecture, and address high-frequency DFT needs while minimizing performance impact, contributing to the

Qualifications

• Experience with design-for-test methodologies, particularly scan test and automatic test pattern generation.

Responsibilities

• Own the generation, validation, and delivery of scan test patterns for next-generation CPU cores and caches.
• Partner with product test teams during test bring-up and troubleshoot pattern, model, and netlist issues.
• Improve scan architecture, scan coverage, test models, execution methods, and overall product quality.
• Perform ATPG pattern and gate-level netlist analysis to identify and resolve testability and coverage issues.
• Collaborate with physical design engineers to support design closure through static timing, clock-domain crossing, netlist, and power analysis.
• Address DFT requirements for high-frequency CPU designs while minimizing performance impact.
• Resolve complex interactions between IP and SoC design environments across global teams.
• Develop and implement improvements that simplify design complexity and strengthen engineering quality.
• Contribute to the continued evolution of CPU cache array and DFT design practices.

Skills

ATPG

Scan test

Pattern generation

Fault coverage

Analytical thinking

Detail-oriented

Cross-functional collaboration

Tools

ATPG tools

Test pattern tools

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

The Cores Organization develops high-performance CPU cores and cache technologies that power AMD’s server, client, and gaming products. We are seeking a DFT/ATPG Design and Test Engineer to support the development and manufacturing readiness of next-generation cores and caches.

In this role, you will own scan test pattern delivery, support product test bring-up, improve scan architecture and coverage, and partner closely with design, physical design, and product test teams to solve complex technical challenges and improve product quality.

THE PERSON:

You are an analytical, detail-oriented engineer who enjoys solving complex technical problems and driving continuous improvement. You take ownership of long-term deliverables, communicate effectively across teams, and challenge established approaches to improve quality and execution. You are eager to expand your knowledge of CPU and cache technologies and thrive in a collaborative environment that values innovation, learning, and technical growth.

KEY RESPONSIBILITIES:

• Own the generation, validation, and delivery of scan test patterns for next-generation CPU cores and caches.
• Partner with product test teams during test bring-up and troubleshoot pattern, model, and netlist issues.
• Improve scan architecture, scan coverage, test models, execution methods, and overall product quality.
• Perform ATPG pattern and gate-level netlist analysis to identify and resolve testability and coverage issues.
• Collaborate with physical design engineers to support design closure through static timing, clock-domain crossing, netlist, and power analysis.
• Address DFT requirements for high-frequency CPU designs while minimizing performance impact.
• Resolve complex interactions between intellectual property and system-on-chip design environments across global teams.
• Develop and implement improvements that simplify design complexity and strengthen engineering quality.
• Contribute to the continued evolution of CPU cache array and DFT design practices.

PREFERRED EXPERIENCE:

• Experience with design-for-test methodologies, particularly scan test and automatic test pattern generation.
• Strong working knowledge of industry-standard ATPG tools and their application to pattern generation, fault coverage, and product quality.