DFT/ATPG Design Engineer - CPU Cores & Cache Testing

OpenTalent; Fort Collins (CO); On-site; USD 110,000 - 170,000; Full time

Job summary

AMD is seeking a DFT/ATPG Design and Test Engineer to support the development and manufacturing readiness of next-generation CPU cores and caches in its Cores Organization. You will own scan test pattern delivery, support test bring-up, and collaborate with design, physical design, and product test teams to improve coverage and quality.

You will analyze gate-level nets, enhance scan architecture, and address high-frequency DFT needs while minimizing performance impact, contributing to the

Qualifications

• Experience with design-for-test methodologies, particularly scan test and automatic test pattern generation.

Responsibilities

• Own the generation, validation, and delivery of scan test patterns for next-generation CPU cores and caches.
• Partner with product test teams during test bring-up and troubleshoot pattern, model, and netlist issues.
• Improve scan architecture, scan coverage, test models, execution methods, and overall product quality.
• Perform ATPG pattern and gate-level netlist analysis to identify and resolve testability and coverage issues.
• Collaborate with physical design engineers to support design closure through static timing, clock-domain crossing, netlist, and power analysis.
• Address DFT requirements for high-frequency CPU designs while minimizing performance impact.
• Resolve complex interactions between IP and SoC design environments across global teams.
• Develop and implement improvements that simplify design complexity and strengthen engineering quality.
• Contribute to the continued evolution of CPU cache array and DFT design practices.

Skills

ATPG

Scan test

Pattern generation

Fault coverage

Analytical thinking

Detail-oriented

Cross-functional collaboration

Tools

ATPG tools

Test pattern tools

Job description

AMD is seeking a DFT/ATPG Design and Test Engineer to support the development and manufacturing readiness of next-generation CPU cores and caches in its Cores Organization. You will own scan test pattern delivery, support test bring-up, and collaborate with design, physical design, and product test teams to improve coverage and quality.

You will analyze gate-level nets, enhance scan architecture, and address high-frequency DFT needs while minimizing performance impact, contributing to the