Design Verification Engineer (Silicon Engineering)

SPACE EXPLORATION TECHNOLOGIES CORP; Redmond (WA); On-site; USD 122,000 - 170,000; Full time

Job summary

A leading company in aerospace is seeking a Design Verification Engineer to work on next-generation FPGAs and ASICs for the Starlink project. The role involves verification, test plan development, and collaboration with cross-disciplinary teams to enhance connectivity solutions globally.

Benefits

Comprehensive medical, vision, and dental coverage

401(k) retirement plan

Paid parental leave

Paid vacation

Paid holidays

Sick leave

Qualifications

• 2+ years of experience with design verification and test bench development.
• Experience with verification methodologies such as UVM.

Responsibilities

• Responsible for digital ASIC and/or FPGA verification at block and system level.
• Write and review test plans, develop test harnesses and test sequences.
• Automate test case generation using Python and MATLAB.

Skills

Problem Solving

Coding

Object-oriented Programming

Education

Bachelor's degree in electrical engineering

Bachelor's degree in computer science

Bachelor's degree in computer engineering

Tools

SystemVerilog

UVM

Python

MATLAB

Job description

Redmond, WA

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal ofenabling human life on Mars.

DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES:

• Responsible for digital ASIC and/or FPGA verification at block and system level
• Write and review test plans, develop test harnesses and test sequences
• Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Automate test case generation by using Python and MATLAB programs
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer science or computer engineering
• 2+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION AND BENEFITS:

Pay range:
Design Verification Engineer/Level I: $122,500.00 - $145,000.00/per year
Design Verification Engineer/Level II: $140,000.00 - $170,000.00/per year

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

• To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here .

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Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out [e-mail] .

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