Silicon Verification Engineer 3

HireTalent; Mountain View (CA); Remote; USD 120,000 - 150,000; Full time

Job summary

A leading company is seeking a Silicon Verification Engineer to join their team on a remote basis. This role involves generating test plans, implementing verification environments, and supporting post-silicon activities for high-speed interfaces in AI and computing projects. The ideal candidate will have extensive experience in SystemVerilog and UVM, along with strong communication and collaboration skills.

Qualifications

• 5-7 years of relevant experience required.
• Experience in pre- and post-silicon verification test flow.

Responsibilities

• Define and implement a UVM verification environment.
• Run tests on RTL and Gate Level Netlists.
• Support post-silicon verification activities.

Skills

Verilog

VMM/OVM/UVM

Effective communication

Collaboration

Teamwork

Education

Bachelor’s degree in Electrical Engineering

Bachelor’s degree in Computer Engineering

Bachelor’s degree in Computer Science

Job description

Job Title: Silicon Verification Engineer 3
Job Location: Remote (PST Time zone)
Job Duration: 3-month contract assignment on a W2 (Possible chances for extension)

Summary:
The main function of a Silicon Verification Engineer is to be a part of the test-plan generation process, creating, testing, and implementing various verification plans.

Job Responsibilities:
• Define, document, and implement a UVM verification environment including agents and scoreboards
• Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral
• Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes
• Support post-silicon verification activities of the products, working with design and product teams

Purpose of the Team: The purpose of this team is IP verification to verify the design of a high-speed interface connecting different parts of an SOC chip.
Key projects: This role will contribute to internal projects that cannot be shared at the moment. They will be working on Certus interfaces and high-speed serial interfaces (CRDAS) for several projects in AI and computing.
Typical task breakdown and operating rhythm: The role will consist of meetings every day in the mornings, which will go over agenda items like tasks and important actions. The remainder of their time is spent heads down focusing on assigned tasks (coding, data analysis, task management).

Skills:
• Proficient in using Verilog and VMM/OVM/UVM
• Experience in pre- and post-silicon verification test flow and automated test benches
• Effective communication, collaboration, and teamwork skills

Education/Experience:
• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related degree required
•5-7 years of relevant experience required.

Candidate Requirements:
Years of Experience Required: 3-7+ (ideally on the higher end) overall years of experience in the field.
Degrees or certifications required: Not required, but nice to have.
Disqualifiers: Candidates must have a strong grasp of SystemVerilog and UVM. If they only have IT experience and are unfamiliar with VMM/ OVM/ UVM, they will not be eligible for the role.
Best vs. Average: The ideal resume would contain previous experience with mixed signal exposure (analog and digital), and is fluent with SystemVerilog and UVM, having significant design verification experience.

Top 3 Hard Skills Required + Years of Experience:
1. Minimum 5+ years of experience with SystemVerilog and UVM.
2. Minimum 5+ years of experience with Mixed Signal Verification.
3. Minimum 5+ years of experience with Design Verification Methodology.