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A leading company is seeking a Senior Design Verification Engineer for remote work. The role involves verifying complex design blocks, developing test plans, and requires strong SystemVerilog and UVM experience. Enjoy long-term contracts with competitive hourly rates and benefits.
Join to apply for the Senior Design Verification Engineer (remote position) role at Correct Designs.
6 days ago Be among the first 25 applicants.
Looking for new challenges? Would you like the variety of a contract position along with long-term stability and benefits? Correct Designs can give it all to you.
Correct Designs is currently seeking talented Verification Engineers with prior SystemVerilog UVM experience to work with our major clients in Austin, TX, and nationwide. Opportunities include projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC products for vision processing, aerospace FPGAs, medical electronics, RISC-V based SoC, ARM peripherals, and mixed signal DSPs. Successful candidates will support verification of advanced CPU/GPU based SOCs.
Correct Designs is not a typical contracting firm. Our engineers enjoy long-term roles with competitive hourly rates in excellent team environments. Contracts typically last around 3 years, with options for shorter or longer durations. We are respected in the Design Verification community, with clients seeking CDI engineers regularly. If you need breaks between contracts, you can take them without losing your place in line for new projects. We also provide healthcare and retirement benefits.
Our base is in Austin, Texas, with clients across the US. Both in-person and remote work are available.
Currently, our positions are filled, but we are continuously looking for skilled CDI engineers. Please submit your resume to be matched with upcoming projects.
Whether you're an experienced veteran or a talented engineer looking to broaden your experience, we offer exciting career options.
Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or Computer Science.