Silicon Verification Engineer 1

Protingent; Mountain View (CA); Remote; USD 150,000 - 200,000; Full time

Job summary

A leading company is seeking a Silicon Verification Engineer 1 for a remote contract position. This role focuses on generating verification plans for advanced chips in AI products. Candidates should have experience in SystemVerilog, UVM, and mixed signal verification. Join a dynamic team and contribute to innovative AI technology.

Benefits

Insurance options (HDHP or POS)

Education/certification reimbursement

Pre-tax commuter benefits

PTO

401k plan

Qualifications

• Minimum of 2+ years’ experience with SystemVerilog and UVM.
• Experience with mixed signal verification.

Responsibilities

• Generate test plans, create and implement verification plans.
• Verify designs of high-speed interfaces for SoC chips.

Skills

SystemVerilog

UVM

Mixed Signal Verification

Design Verification Methodology

Verilog

Effective communication

Job description

Job Description

Position Title: Silicon Verification Engineer 1

Position Description: Protingent has an exciting contract opportunity for a Silicon Verification Engineer 1 with our client located in Mountain View, CA. This role is 100% remote with a high preference for candidates based in PST.

Job Responsibilities:

• The main function of the Silicon Verification Engineer is to be part of the test-plan generation process, creating, testing, and implementing verification plans.
• This role offers the opportunity to work on advanced chips used in AI products.
• Support the development of chips used for AI products, which is a rapidly expanding and interesting field.

Job Responsibilities:

• Verify the design of high-speed interfaces connecting different parts of an SoC chip, focusing on IP verification.
• Contribute to internal projects involving Certus interfaces and high-speed serial interfaces (CRDAS) for AI and compute projects.
• Participate in daily meetings to review tasks and actions; spend remaining time focused on coding, data analysis, and task management.

Job Qualifications:

• Minimum of 2+ years’ experience with SystemVerilog and UVM.
• Experience with Mixed Signal Verification.
• Knowledge of Design Verification Methodology.
• Overall 2+ (preferably 3-6) years of experience in the field.
• Experience with mixed signal (analog and digital) verification, fluent in SystemVerilog and UVM.
• Proficient in Verilog and VMM/OVM/UVM.
• Experience with pre- and post-silicon verification test flows and automated test benches.
• Effective communication, collaboration, and teamwork skills.

Job Details:

• Job Type: Contract
• Location: 100% remote, preference for PST-based candidates
• Pay Range: $39/hr to $47/hr
• Employment contingent on passing a background check.

Benefits Package: Protingent offers competitive salaries, insurance options (HDHP or POS), education/certification reimbursement, pre-tax commuter benefits, PTO, and 401k plan.

About Protingent: Protingent specializes in providing top engineering and IT talent to various industries, aiming to make a positive impact through rewarding work opportunities.