Design Verification Engineer - Power-Aware DV for SoC

MediaTek; Austin, Northern (TX, KY); Hybrid; USD 109,000 - 129,000; Full time

Benefits offered by this job

Health insurance

Life insurance

Disability insurance

Savings plan / 401K

Paid holidays

Sick leave

Vacation time

Parental leave

Job summary

MediaTek USA Inc. in Austin, TX is seeking an Engineer to conduct design verification of complex IP and ARM CPU subsystems, developing DV test plans and DV methodologies.

The role requires collaboration with RTL engineers to resolve issues and perform power-aware simulations using UPF. The ideal candidate holds a Master’s degree in Electrical Engineering and has hands-on experience with SystemVerilog, plus a willingness to learn and contribute to high-performance semiconductor designs with

Qualifications

• Master's degree in Electrical Engineering or related field.
• 0 years of experience required (Experience Requirements: 0 years).
• 3. System Verilog; and

Responsibilities

• Conduct design verification of complex IP and ARM CPU subsystems using latest DV methodologies.
• Develop DV test plans based on specifications and DV strategy to build test benches/infrastructure.
• Provide testing procedures on RTL/GLS/Silicon failures to coordinate with RTL engineers to resolve bugs.
• Setup and run Power Aware simulation using UPF to verify the power integrity of design.
• Develop new DV methodologies.

Skills

System Verilog

Education

Master's degree in Electrical Engineering

Job description

MediaTek USA Inc. in Austin, TX is seeking an Engineer to conduct design verification of complex IP and ARM CPU subsystems, developing DV test plans and DV methodologies.

The role requires collaboration with RTL engineers to resolve issues and perform power-aware simulations using UPF. The ideal candidate holds a Master’s degree in Electrical Engineering and has hands-on experience with SystemVerilog, plus a willingness to learn and contribute to high-performance semiconductor designs with