Design Verification Engineer — Next-Gen AI Silicon, Equity

Platform Recruitment; San Francisco (CA); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Equity

Full benefits

Competitive compensation

Job summary

Platform Recruitment seeks verification engineers to help build scalable silicon for GenAI workloads, spanning compute, memory management and high-speed interconnects. Roles are open across experience levels, with flexibility to move between core verification and tooling.

Ideal candidates will drive verification from architecture through production silicon, employing SystemVerilog, Python and C/C++, UVM and formal methods. The team emphasizes end-to-end ownership from block to tapeout.

Qualifications

• Concept-to-silicon verification from architecture or design spec to production silicon.
• Experience with SystemVerilog, Python and C/C++ for verification and silicon modelling.
• Experience with UVM and assertion-based verification; comfortable with formal and simulation-based methods.
• Experience building portable tests and drivers for silicon validation and post-silicon debug.
• Strong understanding of micro-architecture and high-performance compute, memory management and high-speed connectivity.

Responsibilities

• Shape verification methodology and scalable validation across block, subsystem, full-chip and system levels.
• Own verification execution at subsystem and chip level; build testbenches, tests and artifacts to close coverage.
• Plan and drive verification reviews, test plans, progress reports and sign-off toward tapeout milestones.
• Translate architecture and design specs into production silicon through rigorous verification.

Skills

SystemVerilog

Python

C/C++

UVM

Assertions

Formal verification

Debugging

High-performance compute

Tools

UVM (verification framework)

Formal verification tools

Job description

Platform Recruitment seeks verification engineers to help build scalable silicon for GenAI workloads, spanning compute, memory management and high-speed interconnects. Roles are open across experience levels, with flexibility to move between core verification and tooling.

Ideal candidates will drive verification from architecture through production silicon, employing SystemVerilog, Python and C/C++, UVM and formal methods. The team emphasizes end-to-end ownership from block to tapeout.