Design Verification Engineer

Platform Recruitment; San Francisco (CA); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Equity

Full benefits

Competitive compensation

Job summary

Platform Recruitment seeks verification engineers to help build scalable silicon for GenAI workloads, spanning compute, memory management and high-speed interconnects. Roles are open across experience levels, with flexibility to move between core verification and tooling.

Ideal candidates will drive verification from architecture through production silicon, employing SystemVerilog, Python and C/C++, UVM and formal methods. The team emphasizes end-to-end ownership from block to tapeout.

Qualifications

• Concept-to-silicon verification from architecture or design spec to production silicon.
• Experience with SystemVerilog, Python and C/C++ for verification and silicon modelling.
• Experience with UVM and assertion-based verification; comfortable with formal and simulation-based methods.
• Experience building portable tests and drivers for silicon validation and post-silicon debug.
• Strong understanding of micro-architecture and high-performance compute, memory management and high-speed connectivity.

Responsibilities

• Shape verification methodology and scalable validation across block, subsystem, full-chip and system levels.
• Own verification execution at subsystem and chip level; build testbenches, tests and artifacts to close coverage.
• Plan and drive verification reviews, test plans, progress reports and sign-off toward tapeout milestones.
• Translate architecture and design specs into production silicon through rigorous verification.

Skills

SystemVerilog

Python

C/C++

UVM

Assertions

Formal verification

Debugging

High-performance compute

Tools

UVM (verification framework)

Formal verification tools

Job description

We're working with a well-funded, highly selective AI infrastructure startup building silicon for large-scale AI inference and training. Founded by veteran chip architects who previously led a major AI hardware program at a top tech company, the business has grown fast and is backed by top-tier investors.

They're looking for verification engineers to help build best-in-class silicon for high-performance, sustainable GenAI, across compute, memory management, and high-speed connectivity. They have openings at all levels.

Scope isn't fixed here: they want versatile engineers who can move between core verification and tooling rather than staying in one lane.

Responsibilities

• Shape the verification methodology, building a scalable approach across block, subsystem, full-chip and system-level validation
• Own verification execution at subsystem and chip level, building the testbenches, tests and artifacts needed to close structural and functional coverage
• Plan and drive verification reviews (test plans, execution progress, closure), both intermediate and sign-off, towards milestones including design freeze and tapeout
• Work from architecture and design specifications through to production silicon

Requirements

• Concept-to-silicon experience: you've driven verification from an architecture or design spec through to production silicon
• Working knowledge of SystemVerilog, Python and C/C++ for verification and silicon modelling
• Production experience with UVM and assertion-based verification, and comfort with both formal and simulation-based verification
• Production experience building portable tests and drivers that carry over into silicon validation and post-silicon debug
• Strong grasp of micro-architecture and design concepts in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity and memory management

Nice to Have

• Familiarity with emulation and prototyping platforms and methodologies
• Hands-on participation in silicon debug and bring-up

What Sets This Role Apart

• Real mission: an AI silicon company building best-in-class, power-efficient chips for GenAI, spanning compute, memory management and high-speed connectivity
• Scope from block to system: you're not confined to one level of the stack, and you'll see verification through to tapeout
• Ownership: you take real responsibility for subsystem and chip-level verification, and help define the methodology

Package & Process

Compensation is highly competitive, with strong equity and full benefits.