Design Verification Engineer: IP & High‑Speed Interfaces

Samsung Electronics; United States; Remote; USD 100,000 - 180,000; Full time

Job summary

Samsung Semiconductor India Research (SSIR) seeks a DV engineer for IP/sub-system verification with 3–8 years of experience. You will develop reusable DV components for high-speed interfaces, memory technologies and security, using SV-UVM, formal methods and industry best practices.

Responsibilities include defining coverage, identifying design flaws, and applying automation with Python/Perl to streamline verification of PCIe, AMBA AXI/AHB/APB protocols and related IP blocks.

Qualifications

• 3–8 years of IP/sub-system verification experience.
• Experience with high-speed interfaces such as PCIe and memory techs.
• Knowledge of AMBA protocols (AXI/AHB/APB) and associated IPs.

Responsibilities

• Design and implement reusable DV components for High Speed Interfaces,Security,Memory Technologies
• Create verification components using SV/UVM and Formal methods
• Define and track coverage metrics to identify design flaws
• Collaborate with design teams to verify IP blocks across subsystems

Skills

IP Verification

DV Engineer

UVM

SystemVerilog

Formal Verification

Education

B.Tech/B.E/M.Tech/M.E

Tools

Python

Perl

SV/UVM

Job description

Samsung Semiconductor India Research (SSIR) seeks a DV engineer for IP/sub-system verification with 3–8 years of experience. You will develop reusable DV components for high-speed interfaces, memory technologies and security, using SV-UVM, formal methods and industry best practices.

Responsibilities include defining coverage, identifying design flaws, and applying automation with Python/Perl to streamline verification of PCIe, AMBA AXI/AHB/APB protocols and related IP blocks.