Design Verification Engineer, AI Hardware Systems

OpenAI; California (MO); On-site; USD 120,000 - 180,000; Full time

Job summary

OpenAI is seeking an experienced Design Verification Engineer to verify complex hardware for AI accelerators. You will work across architecture, RTL, software, and systems teams to ensure functional correctness and robust silicon at scale.

You will own verification of IP blocks, subsystems, or full SoC, define plans, build testbenches, and drive regression with high coverage. Collaborative, fast-paced environment with cutting-edge ML hardware.

Qualifications

• BS/MS in EE/CE/CS or equivalent with 3+ years of hardware verification experience.
• Proven experience verifying complex IP or SoC designs in industry-standard flows.
• Strong knowledge of SystemVerilog/UVM and common simulation/debug tools.

Responsibilities

• Own the verification of one or more IP blocks, subsystems, or full-chip SoC functionality.
• Define verification plans based on architecture specs.
• Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM.
• Build and maintain stimulus generators, checkers, monitors, and scoreboards.
• Drive bug triage, root cause analysis, and work with design teams on resolution.
• Contribute to regression infrastructure, coverage analysis, and closure for block- and top-level environments.

Skills

Hardware verification

Education

BS/MS in EE/CE/CS or equivalent

Tools

SystemVerilog

UVM

VCS

Questa

Verdi

Job description

OpenAI is seeking an experienced Design Verification Engineer to verify complex hardware for AI accelerators. You will work across architecture, RTL, software, and systems teams to ensure functional correctness and robust silicon at scale.

You will own verification of IP blocks, subsystems, or full SoC, define plans, build testbenches, and drive regression with high coverage. Collaborative, fast-paced environment with cutting-edge ML hardware.