Design Verification Engineer

OpenAI; California (MO); On-site; USD 120,000 - 180,000; Full time

Job summary

OpenAI is seeking an experienced Design Verification Engineer to verify complex hardware for AI accelerators. You will work across architecture, RTL, software, and systems teams to ensure functional correctness and robust silicon at scale.

You will own verification of IP blocks, subsystems, or full SoC, define plans, build testbenches, and drive regression with high coverage. Collaborative, fast-paced environment with cutting-edge ML hardware.

Qualifications

• BS/MS in EE/CE/CS or equivalent with 3+ years of hardware verification experience.
• Proven experience verifying complex IP or SoC designs in industry-standard flows.
• Strong knowledge of SystemVerilog/UVM and common simulation/debug tools.

Responsibilities

• Own the verification of one or more IP blocks, subsystems, or full-chip SoC functionality.
• Define verification plans based on architecture specs.
• Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM.
• Build and maintain stimulus generators, checkers, monitors, and scoreboards.
• Drive bug triage, root cause analysis, and work with design teams on resolution.
• Contribute to regression infrastructure, coverage analysis, and closure for block- and top-level environments.

Skills

Hardware verification

Education

BS/MS in EE/CE/CS or equivalent

Tools

SystemVerilog

UVM

VCS

Questa

Verdi

Job description

About the Team:

OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.

About the Role

OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting‑edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale.

In this role you will:

• Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC‑level functionality.

• Define verification plans based on architecture and microarchitecture specs.

• Develop constrained‑random, directed, and system‑level testbenches using SystemVerilog/UVM or equivalent methodologies.

• Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.

• Drive bug triage, root cause analysis, and work closely with design teams on resolution.

• Contribute to regression infrastructure, coverage analysis, and closure for both block- and top‑level environments.

You might thrive in this role if you have:

• BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification.

• Proven success verifying complex IP or SoC designs in industry‑standard flows

• Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi).

• Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives.

• Familiarity with performance modeling, formal verification, or emulation is a plus.

• Experience working in fast‑paced, cross‑disciplinary teams with a passion for building reliable hardware.

To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general‑purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.

For additional information, please see OpenAI’s affirmatory Action and Equal Employment Opportunity Policy Statement.

Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US‑based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non‑public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations.

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