Design Verification Engineer

Acceler8 Talent; Mountain View (CA); On-site; USD 200,000 - 320,000; Full time

Job summary

Acceler8 Talent is seeking a Senior Design Verification Engineer in Mountain View, CA (onsite). The role focuses on owning verification for complex IP and subsystems, developing UVM testbenches, and driving coverage closure to ensure silicon success.

You will collaborate with design, architecture, and software teams, build scalable verification environments, and advance verification methodologies with automation and AI-assisted workflows.

Qualifications

• 5+ years of pre-silicon design verification experience.
• End-to-end ownership of verification for complex IP, subsystems, or SoCs.
• Strong UVM methodology and SystemVerilog experience.
• Experience developing verification environments, infrastructure, and reusable test frameworks.
• Proven track record debugging and achieving coverage closure.
• Experience collaborating across hardware and software teams in fast-paced development environments.
• A passion for improving verification methodologies through automation.

Responsibilities

• Own verification for complex IP, subsystems, or SoCs from planning through functional closure.
• Develop UVM testbenches, verification environments, and reusable verification infrastructure.
• Build verification strategies that scale from block-level to full-chip and emulation.
• Debug complex functional issues and drive coverage closure.
• Work closely with design, architecture, and software teams to ensure first-pass silicon success.
• Use AI-assisted verification workflows to improve productivity and speed up development.

Skills

Pre-silicon DV ownership

End-to-end ownership

Automation

Collaboration

Tools

UVM

SystemVerilog

Verification Environments

Emulation Platforms

Job description

Senior Design Verification Engineer

Mountain View, CA (Onsite)

$200,000-$320,000 Base + Equity

I'm working with a stealth AI infrastructure startup founded by the engineers behind Tesla Dojo, Apple Silicon, AMD Zen, and Cerebras.

They're building a fundamentally new computing platform designed to solve one of AI's biggest infrastructure challenges: scaling performance without scaling power consumption and cost.

Using wafer-scale architectures and advanced 3D integration, they're rethinking how AI compute is built from the silicon up, reducing data movement, increasing compute density, and enabling the next generation of AI training and inference.

This is an opportunity to join a small, world-class engineering team building cutting-edge AI hardware from first principles.

You'll work on

• Owning verification for complex IP, subsystems, or SoC components from planning through functional closure
• Developing UVM testbenches, verification environments, and reusable verification infrastructure
• Building verification strategies that scale from block-level verification through full-chip and emulation
• Debugging complex functional issues and driving coverage closure
• Working closely with design, architecture, and software teams to ensure first-pass silicon success
• Using AI-assisted verification workflows to improve productivity and accelerate development

We're looking for engineers who have

• 5+ years of pre-silicon design verification experience
• End-to-end ownership of verification for complex IP, subsystems, or SoCs
• Strong UVM methodology and SystemVerilog experience
• Experience developing verification environments, infrastructure, and reusable test frameworks
• A proven track record driving functional debug and coverage closure
• Experience collaborating across hardware and software teams in fast-paced development environments
• A passion for improving verification methodologies through automation and modern engineering tools

Particularly relevant experience includes

• Design Verification
• SystemVerilog
• UVM
• SoC Verification
• Block-Level Verification
• Functional Verification
• Coverage Closure
• Emulation
• AI Accelerators
• Networking or Datacenter Silicon

Nice to have

• CPU, GPU, AI accelerator, or datacenter silicon experience
• DMA or NoC verification
• Multi-die or chip-to-chip protocol verification
• RISC-V architecture
• Formal verification
• Experience with Palladium, Veloce, or similar emulation platforms
• Post-silicon bring-up experience

If you're looking to build verification infrastructure, not just write tests, and want to help develop the next generation of AI hardware alongside some of the industry's leading silicon engineers, I'd love to chat.