Design Verification Engineer

Apple; Waltham (MA); On-site; USD 120,000 - 180,000; Full time

Job summary

An innovative industry leader is seeking a dedicated Design Verification Engineer to join their dynamic team in Waltham, Massachusetts. This role offers a unique chance to work on cutting-edge technology and create products that enhance the lives of millions. You will be responsible for ensuring the quality of first silicon for complex SoC and IP designs, developing verification methodologies, and executing comprehensive test plans. If you thrive on solving complex challenges and have a passion for technology, this opportunity could be your next big step in a rewarding career.

Qualifications

• 10+ years of experience in design verification engineering.
• Strong knowledge of OOP, SystemVerilog, and UVM methodologies.

Responsibilities

• Ensure bug-free first silicon for SoC/IP designs.
• Develop verification methodology and execute verification plans.

Skills

OOP

SystemVerilog

UVM

Python

Perl

TCL

Power-aware verification (UPF)

Serial protocols (PCIe, USB)

Parallel protocol (DDR)

Formal verification methodology

Education

BS degree in technical subject area

Tools

Simulators

Waveform viewers

Build and run automation

Coverage collection

Gate level simulations

Job description

Design Verification Engineer

Waltham, Massachusetts, United States Hardware

Summary

Posted: Dec 20, 2024

Role Number: 200574760

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers daily. This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Description

In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Furthermore, you will develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring-up, regression enabling features, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage.

Minimum Qualifications

1. BS degree in technical subject area with minimum 10 years of proven experience.

Preferred Qualifications

1. Solid knowledge of OOP, SystemVerilog, and UVM.
2. Solid knowledge in developing scalable and portable test-benches.
3. Relevant experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, gate level simulations.
4. Experience with power-aware (UPF) or similar verification methodology.
5. Excellent knowledge of one of the scripting languages such as Python, Perl, TCL.
6. Experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required.
7. Knowledge of formal verification methodology is a plus but not required.