Design Verification Engineer

Apple Inc.; Waltham (MA); On-site; USD 80,000 - 130,000; Full time

Job summary

An established industry player is seeking a Design Verification Engineer to ensure high-quality silicon for innovative SoC and IP designs. In this pivotal role, you will craft detailed test and coverage plans, develop scalable verification environments, and implement robust methodologies. Collaborating with a talented team, you will tackle complex verification challenges, ensuring that every aspect of the design meets the highest standards. This is a fantastic opportunity to enhance your expertise in verification methodologies and tools while contributing to cutting-edge technology in a dynamic and inclusive workplace.

Qualifications

• Minimum 3 years of relevant industry experience or equivalent.
• Knowledge of verification methodologies and tools is essential.

Responsibilities

• Ensure bug-free first silicon for SoC / IP through detailed test plans.
• Develop verification environment including stimulus, checkers, and trackers.

Skills

Object-Oriented Programming (OOP)

SystemVerilog

UVM

Scripting languages (Python, Perl, TCL)

Debugging

Education

BS degree in technical subject area

Tools

Simulators

Waveform viewer

Build and run automation tools

Coverage collection tools

Gate level simulations

Job description

Waltham, Massachusetts, United States Hardware

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Description

In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop a verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, and coverage. Furthermore, you will learn to develop verification plans for all features under your care, implement verification plans, including design bring-up, DV environment bring-up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP, and SoC level test-benches, track and report DV progress using a variety of metrics, including bugs and coverage.

Minimum Qualifications

• BS degree in technical subject area and a minimum 3 years relevant industry experience or equivalent

Preferred Qualifications

• Working knowledge of OOP, SystemVerilog and UVM
• Working knowledge in developing scalable and portable test-benches
• Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate level simulations
• Experience with power-aware (UPF) or similar verification methodology
• Knowledge of one of the scripting languages such as Python, Perl, TCL
• Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
• Knowledge of formal verification methodology is a plus but not required

Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.