Senior FPGA Design Verification Engineer

ZipRecruiter; Dedham (MA); On-site; USD 120,000 - 150,000; Full time

Job summary

A leading company is seeking a Senior FPGA Design Verification Engineer in Dedham, MA. The role involves product design from system architecture to production, requiring extensive experience in FPGA design verification and a collaborative spirit. The company offers a supportive work environment with a focus on innovation and employee development.

Benefits

401k matching

Flex time off

Paid parental leave

Healthcare benefits

Health & wellness programs

Qualifications

• Minimum 8 years experience with Bachelor's or 6 years with Master's.
• Experience with OVM/UVM design verification methodology.

Responsibilities

• Member of cross-functional team for product design and release.
• Analyze requirements and create test plans for complex FPGAs.

Skills

OVM

UVM

Python

VHDL

SystemVerilog

Education

Bachelor’s degree in Electrical or Computer Engineering

Master's degree in relevant field

Tools

Xilinx FPGA

Questa Advanced Functional Verification

Job description

Job Description

Career Renew is recruiting for one of its clients a Senior FPGA Design Verification Engineer in Dedham, MA.

Our engineers redefine what’s possible and our manufacturing team brings it to life, building the brains behind the brawn on submarines, ships, combat vehicles, aircraft, satellites, and other advanced systems.

We pride ourselves in being a great place to work with this shared sense of purpose, committed to a diverse and exciting employee experience that drives innovation and creates a community where all feel welcome and a part of something amazing.

As a Senior Cyber FPGA Design Verification engineer, you’ll be a member of a cross functional team responsible for product design from system architecture & requirements allocation through product release and production of cost-sensitive secure products.

Requirements

• Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 8 years of relevant experience; or Master's degree plus a minimum of 6 years of relevant experience.
• Experience with OVM / UVM design verification methodology: bash/csh, Perl, TCL, Python or similar scripting; VHDL or similar hardware description language.
• Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. U.S. citizenship is required due to the nature of work performed within our facilities.

What sets you apart:

• Experience defining verification methodology for complex FPGAs.
• Ability to analyze requirements, create test plans, and build scalable simulation environments using SystemVerilog/UVM.
• Familiarity with testing complex designs, code coverage, functional coverage, assertions.
• Ability to work in a dynamic environment with changing needs and requirements.
• FPGA/ASIC design experience is a plus.
• Familiarity with Xilinx FPGA & Questa Advanced Functional Verification tools is a plus.
• Team player who thrives in collaborative environments and celebrates team success.

Benefits

• An exciting career path with opportunities for continuous learning and development.
• Research-oriented work alongside award-winning teams developing practical solutions for our nation’s security.
• Flexible schedules with every other Friday off (9/80 schedule).
• Competitive benefits, including 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs, employee resource and social groups, and more.