Design Verification Engineer

Eximietas Design; Santa Clara (CA); On-site; USD 114,000 - 133,000; Full time

Job summary

Join a pioneering firm in semiconductor innovation as a Design Verification Engineer. This role offers the chance to work on cutting-edge SmartNICs and high-speed switch ASICs, validating performance-critical components for modern cloud and data center infrastructure. With a focus on ASIC/SoC design verification, you'll develop advanced testbenches and collaborate with top-tier teams to ensure robust functionality. This is an exciting opportunity to contribute to the future of networking silicon in a dynamic and innovative environment.

Qualifications

• 5+ years in ASIC/SoC Design Verification with strong SystemVerilog/UVM skills.
• Deep understanding of networking protocols like Ethernet and TCP/IP.

Responsibilities

• Develop UVM/SystemVerilog testbenches for advanced networking SoCs.
• Collaborate with design and software teams for robust functionality.

Skills

ASIC/SoC Design Verification

SystemVerilog

UVM

Networking Protocols

Python

Perl

Shell Scripting

Education

Bachelor's Degree in Electrical Engineering

Master's Degree in Computer Science

Tools

FPGA

Veloce

Palladium

Job description

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At Eximietas Design, we’re pushing boundaries in semiconductor innovation—and we're building a top-tier team of Design Verification Engineers focused on networking silicon. This is your opportunity to work on cutting-edge SmartNICs, DPUs, and high-speed switch ASICs, validating some of the most performance-critical components in modern cloud and data centre infrastructure.

What You’ll Work On

• Develop UVM/SystemVerilog testbenches for advanced networking SoCs.
• Verify critical networking blocks such as:
• Ethernet MAC/PHY (1G/10G/100G/400G)
• VLAN, QoS, multicast, and traffic-shaping logic
• Drive coverage closure, assertion-based verification (SVA), and scoreboarding.
• Collaborate with design, architecture, and software teams to ensure robust functionality.
• Contribute to full-system validation using simulation, emulation, or FPGA platforms.

What We’re Looking For

• 5+ years of experience in ASIC/SoC Design Verification.
• Deep understanding of networking protocols: Ethernet, TCP/IP, VLAN, routing, switching.
• Strong expertise in SystemVerilog/UVM, functional coverage, and debugging.
• Experience with packet processing logic, buffers, schedulers, and routing engines.
• Proficiency in scripting (Python, Perl, Shell) for automation and regression flows.

Bonus Points For

• Prior work on SmartNICs, DPUs, or network switch/router silicon.
• Hands-on with emulation (Veloce, Palladium, Zebu) or FPGA-based prototyping.
• Familiarity with L2/L3 ECMP, multicast, and programmable pipelines.
• Background at companies like Broadcom, Marvell, NVIDIA, Cisco, Intel, or similar.
• Build next-generation networking chips from the ground up.
• Work with an elite team of DV and architecture experts.
• Tackle real packet-level verification challenges that impact global infrastructure.
• Competitive compensation, benefits, and a strong engineering culture.

Ready to Apply?

Reach out directly at [e-mail]

Visit us at www.eximietas.design

Let’s build the future of networking silicon – together.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Information Technology

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