Design Verification Engineer

Nanojoules; United States; Remote; USD 80,000 - 120,000; Full time

Job summary

An established industry player in semiconductor technology is seeking a Design Verification Engineer to join their innovative team. In this role, you will engage in the functional verification of SOC/IP logic, ensuring designs meet rigorous specifications. Collaborating closely with architects and RTL developers, you will develop verification plans, execute system simulations, and troubleshoot issues in a dynamic environment. This is a fantastic opportunity to work alongside world-class engineers, tackle challenging problems, and contribute to cutting-edge projects in consumer electronics and green energy applications. If you're passionate about technology and eager to grow, this role could be your next big step.

Benefits

Steep learning curve

Competitive salary

Company equity

Full medical benefits

Flexibility to work remotely

Qualifications

• 3-5 years of experience in verification of design blocks and SoC components.
• Knowledge of scripting and familiarity with AMBA standards is a plus.

Responsibilities

• Perform functional verification of SOC/IP logic to ensure design meets specifications.
• Develop verification plans and maintain existing verification infrastructure.

Skills

System Verilog

OVM

UVM

Debugging

Analytical Skills

Problem-Solving

Education

Bachelor in Electrical Engineering

Master in Electrical Engineering

Tools

Verification Environment

Test Benches

Simulation Models

Job description

About Company

Nanojoules Semiconductors is a true Fabless company building indigenous next gen chips with focus on consumer electrical, Electric vehicle (EV), green energy applications and high performance compute.

We are building a world class silicon design team and looking for passionate engineers who get excited by opportunities to solve hard problems, believe in working on the first principles and have the longing to innovate and build products.

Job Title: Design Verification Engineer

Job Description:

• Performs functional verification of SOC/IP logic to ensure design will meet specification requirements.
• Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.
• Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.
• Replicates, root causes, and debugs issues in the presilicon environment.
• Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
• Maintains and improves existing functional verification infrastructure and methodology.

Required Qualifications and experience:

• Bachelors / Masters in EE /ECE with 3-5 years of experience
• Highly motivated and energetic with strong inclination to learn and grow.
• Experience in verification of design blocks (IP) and SoC components
• Experience in system verilog, and/ OVM or UVM methodologies.
• Experience in one/more of the following areas is a plus: Debug, Connectivity IPs and /or AMBA standards (OCP, AXI, AHB etc.)
• Knowledge of scripting, SV is a plus.

Soft Skills:

• Good written and verbal communication skills.
• Start-up mentality: fast-paced, flexible and team-oriented.
• Strong mathematical, analytical, problem-solving, and hands-on skills.
• Self-driven and thrives when facing open-ended tasks.
• Flexibility to work with varied schedules and tolerance for ambiguity.

Perks and benefits:

• Work with world class engineers and experience a Steep learning curve
• Competitive salary and Company equity to the deserving ones.
• Flexibility to work remotely
• Full medical benefits for you and your family (100% covered)