Design Verification Architect

TYLsemi; United States; Remote; USD 180,000 - 250,000; Full time

Job summary

TYLsemi is seeking a highly experienced Design Verification Architect to lead scalable verification strategies for AI, HPC, and Networking SoCs. The role emphasizes automation, portability, and AI-driven methodologies to enable first-pass silicon success.

You will define the overall verification architecture, develop portable platforms, and drive UVM-based testbenches across block-to-full-chip levels, while mentoring DV teams and collaborating with design and software groups.

Qualifications

• 12+ years of experience in Design Verification
• Experience in large SoC verification
• Strong SystemVerilog and UVM expertise
• Experience with Portable Stimulus (PSS) and cross-level stimulus reuse
• Deep understanding of SoC architectures in AI, HPC, or Networking domains
• Experience with multi-IP integration challenges, coherency, high-speed interfaces
• Strong debugging skills and ability to handle complex system-level issues

Responsibilities

• Define and drive the overall verification architecture for large-scale SoCs
• Architect and develop reusable, modular verification platforms
• Establish methodologies for seamless reuse and portability, including PSS-based verification
• Lead the development of high-performance, coverage-driven testbenches using UVM
• Drive multi-level verification strategies across block, multi-block, and full-chip levels
• Mentor and guide DV teams on best practices and methodology adoption

Skills

SystemVerilog

UVM

Coverage-driven verification

Assertion-based verification

Portable Stimulus

AI/ML in verification

Multi-IP integration

Debugging

Architectural thinking

Education

Bachelor’s/Master’s degree in Electrical Engineering or Computer Engineering

Job description

Role Overview

We areseekinga highly experienced Design Verification Architect to lead the definition and execution of scalable, reusable, and high-quality verification strategies for next-generation SoCs targeting AI, HPC, and Networking applications. This role requires deepexpertisein verifying large and complex SoCs and a passion for building next-gen verificationplatforms,leveraging automation, portability, and AI-driven methodologies.

WhatYou’llDo

• Define and drive the overall verification architecture for large-scale SoCs, ensuring scalability from IP subsystem full SoC level
• Architect and develop reusable, modular, and portable verification platforms that can beleveragedacross multiple chip programs
• Establish methodologies for seamless reuse and portability , includingPortable Stimulus (PSS)-based verification flows
• Lead the development of high-performance, coverage-driven testbenches using industry-standard methodologies (e.g., UVM)
• Drive multi-level verification strategies , enabling efficient scaling across:
• Block-level, Multi-block/subsystem level, Full-chip SoC level
• Define and enforce verification quality metrics , coverage closure strategies, and sign-off criteria
• Champion a “fail-fast” philosophy to detect issues early and improve overall design quality
• Drive initiatives toward first-pass silicon success , minimizing escapes and post-silicon debug effort
• Leverage AI/ML techniques and AI agents to:
• Automate testbench generation
• Improve stimulus generation and coverage closure
• Enhance regression efficiency and debug productivity
• Enable intelligent verification QA and anomaly detection
• Collaborate closely with design, architecture, physical design, and software teams to ensure alignment and early issue detection
• Mentor and guide DV teams on best practices, methodology adoption, and architectural decisions

WhatWe’reLooking For

• Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or related field
• 12+ years of experience in Design Verification , with significant exposure to large SoC verification
• Proven experience in defining and deploying verification architectures for complex chips
• Strongexpertisein:
• SystemVerilogand UVM
• Coverage-driven verification (functional + code coverage)
• Assertion-based verification (SVA)
• Hands-on experience withPortable Stimulus (PSS)and cross-level stimulus reuse
• Deep understanding of SoC architectures in AI, HPC, or Networking domains
• Experience with multi-IP integration challenges , coherency, high-speed interfaces, and large-scale data movement
• Strong debugging skills and ability to handle complex system-level issues

Preferred Qualifications

• Experience with AI/ML applications in verification workflows
• Exposure to emulation, prototyping, or hybrid verification platforms
• Familiarity with performance verification and power-aware verification
• Knowledge of industry-standard protocols (e.g., PCIe, DDR, Ethernet, CXL, UCIe)
• Experience building verification frameworks reused across multiple tape-outs

Key Attributes

• Strong architectural thinking with a systems-level mindset
• High ownership with a quality-first approach
• Bias toward automation, reuse, and scalability
• Passion for adopting cutting-edge technologies , especially AI-driven verification
• Ability tooperatein a fast-paced environment with a fail-fast, learn-fast attitude
• Excellent collaboration and leadership skills

Success in This Role Looks Like

• High degree of verification reuse across programs
• Achievement of coverage and quality goals within schedule
• Reduction in verification cycle time through automation and AI
• Strongtrack recordof first-time silicon success
• Minimal post-silicon escapes and debug cycles