Design Verification Engineer

Pyramid Consulting, Inc; San Francisco (CA); On-site; USD 160,000 - 170,000; Full time

Benefits offered by this job

Health insurance

401(k) plan

Paid sick leave

Job summary

Pyramid Consulting, Inc. has an immediate Design Verification Engineer opening in San Francisco, CA. This onsite, fulltime role offers long-term potential with competitive pay and comprehensive benefits.

The ideal candidate brings 6+ years in verification of digital and mixed-signal circuits, SystemVerilog/UVM/SVA expertise, and experience with major EDA tools. A BS or MS in EE/CE with relevant experience is required.

Qualifications

• 6+ years of experience with verification concepts for complex digital and mixed-signal circuits
• Experience verifying designs at block and system levels
• Proficiency with SystemVerilog and advanced verification methodologies (UVM, SVA)
• Experience with Synopsys, Cadence, and Mentor simulation tools
• Proficient in Perl/Python and Tcl scripting languages
• Strong writing, grammar, and verbal communication skills
• Ability to work independently and in a global, dynamic environment
• Legal authorization to work in the US

Responsibilities

• Plan and deploy complex, reusable verification environments
• Verify designs at block and system levels to ensure correct functionality
• Debug RTL and gate-level netlists and analyze schematic diagrams of analog/mixed-signal circuits
• Collaborate with global teams and adapt to new tools and methodologies

Skills

Design verification concepts

SystemVerilog/UVM/SVA

RTL/gate-level debugging

Scripting: Python/Perl/Tcl

Version control (git/DesignSync)

Communications skills

Independent/global team work

Education

BS in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

Tools

Synopsys

Cadence

Mentor Graphics

DesignSync

Git

Job description

Immediate need for a talented Design Verification Engineer . This is a Fulltime opportunity with long-term potential and is located in San Francisco, CA (Onsite).

Job ID:26-19462

Pay Range: $160000 - $170000/annum. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location).

Key Requirements and Technology Experience:

• 6+ years of experience with verification concepts and architectures for complex digital and MXS circuits
• Experience verifying designs at the block and system levels.
• Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)
• Experience debugging RTL and gate-level netlists, analyzing schematic diagrams of analog / MXS circuits
• Experience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)
• Experience with Synopsys, Cadence, and Mentor simulations tools
• Demonstrated ability to plan and deploy complex, reusable, and scalable verification environments
• Experience with Perl/Python and Tcl or other scripting languages
• Experience with version control systems (DesignSync, git)
• Superior writing, grammar, and verbal communication skills
• Excellent problem solver; develops and employs automated processes where applicable
• Worked independently and in a global team and dynamic environment in a highly visible role
• Possesses ability to learn and adapt to new tools and methodologies on the fly
• Must have legal authorization to work in the US.
• BS in Electrical Engineering / Computer Engineering and 8+ years of related experience or an MS in Electrical Engineering / Computer Engineering and 6+ years of related experience.
• And (SystemVerilog OR UVM OR SVA)
• And (PLL OR DLL OR ADC OR DAC OR "mixed signal")
• And (Synopsys OR Cadence OR Mentor)
• And (Python OR Perl OR Tcl)

Our client is a leading IT Industry, and we are currently interviewing to fill this and other similar fulltime positions.

Pyramid Consulting, Inc. provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.