Design Verification (DV) Lead

Carman Solutions Group; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Carman Solutions Group in Sunnyvale, CA is seeking a Design Verification Lead (Managerial level) for an onsite full-time role. You will develop and drive verification strategies and collaborate with Design, Model, Emulation and Silicon teams.

Requires 10+ years in DV, constrained-random and coverage-driven verification, C/C++ and experience with EDA tools and scripting (Python, TCL, Perl, Shell). This role emphasizes leadership in verification and cross-functional collaboration.

Qualifications

• 10+ years of experience in design verification
• Strong knowledge of constrained-random and coverage-driven verification methodologies
• Experience verifying an IP block using DV techniques
• Proficient with EDA tools and scripting for verification environments

Responsibilities

• Develop verification plans and testbenches to drive verification closure
• Drive verification metrics and test coverage to meet plan goals
• Debug failures and perform root-cause analysis with design/architecture teams
• Collaborate with Design, Model, Emulation and Silicon validation teams to ensure design quality

Skills

Constrained-random verification

Coverage-driven verification

C/C++ verification

Tools

EDA tools

Python

TCL

Perl

Shell

Job description

Sunnyvale, CA, USA Onsite

Visa- G C and U S C only

What You Will Do

Develop functional tests based on verification test plan

• Drive Design Verification to closure based on defined verification metrics on test
• plan, functional and code coverage
• Debug, root-cause and resolve functional failures in the design, partnering with
• the design/arch team
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon
• validation teams towards ensuring the highest design quality

Design Verification (DV) Lead (Managerial level)

Fulltime

What You Will Bring

Experience :10+ years

• Experience using constrained-random, coverage driven verification or C/C++
• verification
• Experience in verifying a IP block using standard Design Verification (DV) based
• techniques
• Experience in Electronic Design Automation (EDA) tools and scripting
• (Python, Tool Command Language (TCL), Perl, Shell) used to build tools and
• flows for verification environments
• Understanding in at least one of the following areas: computer architecture,
• Central Processing Unit (CPU), Graphics Processing Unit
• (GPU), networking, interconnects, fabrics or similar designs
• Experience debugging fails to the line of RTL, closing out bug fixes,
• using Verdi or equivalent debug tools
• Experience with revision control systems like Mercurial (Hg), Git or SVN
• Experience working in a CPU/GPU environment