ASIC Physical Design Engineer - DFT, Senior

positron.ai; Stati Uniti; Remoto; USD 180.000 - 240.000; Tempo pieno

Vantaggi offerti da questo lavoro

Remote-first setup

Medical, dental, vision coverage

Life and disability coverage

401(k) matching

Unlimited PTO

13 holidays

Salary and equity

Descrizione del lavoro

positron.ai is seeking a hands-on Lead DFT engineer to drive test-for-chip strategy for custom AI accelerators. You will own DFT architecture from RTL through tapeout, coordinating with backend teams and performing pre-silicon validation, simulation, and verification.

You will implement scan insertion, ATPG, memory BIST, boundary scan, and IJTAG, while planning test coverage and collaborating across RTL, synthesis, and physical design to ensure a successful silicon bring-up.

Competenze

• Significant hands-on experience implementing DFT for complex ASICs or SoCs.
• Experience with RTL, synthesis, DFT tools, and simulation or gate-level verification.
• Ability to collaborate with backend teams and carry DFT work through tapeout.

Mansioni

• Design and implement scan, compression, ATPG, memory BIST, boundary-scan, IJTAG, and debug or observability features.
• Integrate DFT logic into internal RTL and assess test capabilities in third-party IP.
• Develop verification plans and validate DFT behavior through simulation and gate-level checks.
• Plan stuck-at, transition, cell-aware, and power-aware ATPG strategies and meet test coverage goals before tapeout.
• Work with physical design teams on scan-chain partitioning, compression, test clocks, and physical implementation.
• Support silicon test and bring-up, investigating issues and improving test readiness.

Conoscenze

Hands-on DFT

RTL development

Pre-silicon verification

Collaboration

Strumenti

ATPG tools

Synthesis tools

Boundary scan tools

IJTAG tools

Simulation tools

Descrizione del lavoro

Role overview

Lead design-for-test implementation for custom AI accelerator chips, owning the work from DFT architecture through tapeout and initial silicon bring-up. This is a hands-on engineering role spanning RTL, synthesis, test flows, pre-silicon validation, and coordination with backend implementation teams.

Responsibilities

• Design and implement scan, compression, ATPG, memory BIST, boundary-scan, IJTAG, and debug or observability features.
• Integrate DFT logic into internal RTL and assess test capabilities in third-party IP.
• Develop verification plans and validate DFT behavior through simulation and gate-level checks.
• Plan stuck-at, transition, cell-aware, and power-aware ATPG strategies and meet test coverage goals before tapeout.
• Work with physical design teams on scan-chain partitioning, compression, test clocks, and physical implementation.
• Support silicon test and bring-up, investigating issues and improving test readiness.

Requirements

• Significant hands-on experience implementing DFT for complex ASICs or SoCs.
• Practical knowledge of scan insertion, ATPG, memory BIST, boundary scan, and IJTAG.
• Experience working with RTL, synthesis, DFT tools, and simulation or gate-level verification.
• Ability to collaborate with backend teams and carry design-for-test work through tapeout.

Benefits and work setup

Remote-first work includes a company-provided computer and home-office setup.

Benefits include fully paid medical, dental, and vision coverage for employees and dependents, life and disability coverage, optional supplemental insurance, unlimited paid time off, 13 company holidays, salary and equity, and a matching 401(k).

Applicants need current U.S. work authorization; eligible H-1B transfers may be facilitated, but new sponsorship is unavailable.