Senior Principal Digital Design Engineer

Cadence Design Systems, Inc.; San Jose (CA); On-site; USD 154,000 - 286,000; Full time

Job summary

Cadence Design Systems, Inc. in San Jose, CA seeks a Senior Principal Digital Design Engineer to design, develop, and support system-level memory IP models used in hardware-based verification products.

You will work across SDRAM, NAND, eMMC, DFI, UFS, and related interfaces with strong RTL design and debugging skills. You will collaborate with internal and external customers on emulation, simulation, and verification challenges, creating documentation and advancing product quality across the

Qualifications

• MS/EE or equivalent with substantial experience in protocols, RTL and hardware systems.
• 5+ years designing complex RTL/protocols.
• Strong Verilog/SystemVerilog RTL design experience and debugging skills.
• Excellent English written and verbal communication.

Responsibilities

• Design, develop, verify, and productize memory IP models for hardware verification platforms.
• Develop models for LPDDR, HBM, NAND Flash, eMMC, SD Card, DFI, UFS.
• Maintain and enhance existing memory IP products.
• Develop RTL using Verilog/SystemVerilog with sound coding practices.
• Plan verification strategies using standard simulation and emulation tools.
• Debug complex RTL, protocols, systems, and customer issues to root causes.
• Create and maintain technical memory IP documentation.
• Collaborate with customers to understand requirements and provide solutions.
• Manage project schedules, priorities, and deliverables in an agile environment.
• Collaborate across memory IP products for cross-verification and knowledge sharing.
• Help evolve engineering processes for quality and maintainability.
• Identify risks and drive resolution.

Skills

Verilog/SystemVerilog RTL design

RTL verification methodologies

debugging complex hardware

English communication

planning and scheduling

collaboration across teams

root-cause analysis

Education

MSEE or equivalent

Tools

Cadence simulation

emulation platforms

Perl

Tcl/Tk

Job description

SAN JOSE

Full time

R55165

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Overview

As a Senior Principal Digital Design Engineer, you will be responsible for the design, development, and ongoing support of system‑level memory IP models used in hardware‑based verification products.

You will work across a broad range of memory technologies and interfaces, including SDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS. In addition to developing new memory models, you will maintain and enhance existing products to ensure performance, quality, usability, and long‑term customer support.

This role is a highly collaborative individual‑contributor position that requires strong RTL design and verification expertise, excellent debugging skills, and the ability to work directly with internal and external customers on complex emulation, simulation, and verification challenges.

Key Responsibilities

• Design, develop, verify, and productize system‑level memory IP models for hardware‑based verification platforms.

• Develop memory models supporting technologies and interfaces such as LPDDR, HBM, NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS.

• Maintain, enhance, debug, and support existing memory IP products throughout their lifecycle.

• Develop high‑quality RTL using Verilog/SystemVerilog, applying sound design and coding practices.

• Develop and execute verification strategies using industry‑standard simulation and emulation tools and methodologies.

• Diagnose and resolve complex RTL, protocol, system, and customer issues through effective debugging and root‑cause analysis.

• Create and maintain technical documentation for memory IP, including design specifications, user documentation, and product support materials.

• Work directly with internal and external customers to understand requirements, investigate issues, and develop effective solutions for emulation, simulation, and verification environments.

• Plan and manage individual project schedules, priorities, deliverables, and technical tasks while adapting to changing business and customer needs.

• Collaborate with cross‑functional engineering teams to support cross‑verification, knowledge sharing, and cross‑training across memory IP products.

• Contribute to and help evolve engineering lifecycle processes, methodologies, and quality practices to ensure reliable, maintainable, and high‑quality products.

• Proactively identify technical risks and opportunities for improvement and drive issues to resolution.

Required Qualifications

• MSEE or equivalent advanced degree with a minimum of 5 years of significant experience designing complex protocols, RTL, and/or hardware systems.

• Extensive hands‑on experience with Verilog/SystemVerilog RTL design.
• Strong understanding of RTL verification methodologies, tools, and flows.
• Demonstrated ability to debug complex hardware, RTL, protocol, and system‑level issues.
• Strong analytical and problem‑solving skills, with the ability to identify root causes and develop practical solutions.
• Excellent written and verbal communication skills in English.
• Proven ability to work effectively as an individual contributor while collaborating closely with engineering, product, and customer‑facing teams.
• Strong organizational and planning skills, with the ability to manage multiple priorities, schedules, and deliverables in an agile and adaptive environment.
• High emotional intelligence and a collaborative approach to communication, problem‑solving, and conflict resolution.
• Preferred Qualifications
• Experience with Cadence simulation and/or emulation products.
• Experience with hardware emulation, simulation, or other hardware‑based verification platforms.
• Programming or scripting experience with Perl, Tcl/Tk, C‑shell, or similar languages.
• Experience with memory subsystem architecture, design, and operation.
• Experience designing or verifying memory protocols such as LPDDR, HBM, NAND Flash, eMMC, SD, DFI, or UFS.
• Experience developing reusable IP models or verification components for complex SoC or system‑level environments.

What Success Looks Like

Success in this role means delivering robust, reusable, and customer‑ready memory IP models while continuously improving existing products. You will combine deep RTL and verification expertise with strong debugging, communication, planning, and collaboration skills to solve challenging problems and help advance the quality and capabilities of the overall memory IP portfolio.

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.