DDR PHY System Architect - High-Performance, Low-Power

Qualcomm; San Diego (CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Annual discretionary bonus program

RSU grants

Competitive benefits package

Job summary

Qualcomm seeks a skilled system architect in San Diego to design high-speed, high-performance DDR PHYs aimed at 5G, AI/ML, and automotive applications. This role involves the full design process from conceptualization to final chip production.

Ideal candidates will have experience in DDR PHY design, a strong grasp of JEDEC standards, and excellent communication skills. Competitive pay ranges from $140,000 to $210,000, along with comprehensive benefits.

Qualifications

• 5-10 years in DDR PHY system design/architecture required.
• Strong knowledge of link budgets and training is necessary.
• Experience with signal integrity and power delivery preferred.

Responsibilities

• Analyze and own DDR PHY system and architecture.
• Develop system timing budgets, both on-die and off-chip.
• Lead and deliver solutions for product needs.

Skills

DDR PHY system design/architecture

Knowledge of JEDEC DDR standards

Strong communication skills

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

Unix

Perl

TCL scripting

Job description

Qualcomm seeks a skilled system architect in San Diego to design high-speed, high-performance DDR PHYs aimed at 5G, AI/ML, and automotive applications. This role involves the full design process from conceptualization to final chip production.

Ideal candidates will have experience in DDR PHY design, a strong grasp of JEDEC standards, and excellent communication skills. Competitive pay ranges from $140,000 to $210,000, along with comprehensive benefits.