DDR PHY SI/PI Engineer for System-Level Validation

Saicon; Santa Clara (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Saicon is seeking an experienced signal integrity and power integrity engineer to join the CT Server DDR team in Santa Clara, CA. You will own DDR PHY channel and PDN architecture, model system-level SI/PI, and validate results on silicon.

You will collaborate with design, package, board and firmware teams to specify SI/PI targets, implement solutions, and debug issues across the full system stack, including post-silicon data analysis and ATE firmware considerations.

Qualifications

• Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.
• Hands-on in defining channel and PDN architectures and validating SI/PI against silicon.
• Experience with post-silicon validation and cross-functional collaboration.

Responsibilities

• Run system-level channel and PDN simulations (insertion/return loss, crosstalk, eye diagrams, impedance, IR drop, jitter transfer) and correlate with silicon results.
• Process post-silicon SI/PI validation data and drive next steps.
• Debug SI/PI issues across silicon, package, and board with firmware and design teams.
• Support cross-functional teams with system, channel, PDN, and decoupling implementation details.

Skills

Python

MATLAB

SI/PI knowledge

S-parameter analysis

Channel modeling

PDN modeling

Firmware debugging

Silicon-to-simulation correlation

Education

Bachelor's degree in Computer/Electrical Engineering

Master's degree in Electrical/Computer Engineering

Tools

HFSS

SIwave

Sigrity

Clarity

Ansys

Cadence

Job description

Saicon is seeking an experienced signal integrity and power integrity engineer to join the CT Server DDR team in Santa Clara, CA. You will own DDR PHY channel and PDN architecture, model system-level SI/PI, and validate results on silicon.

You will collaborate with design, package, board and firmware teams to specify SI/PI targets, implement solutions, and debug issues across the full system stack, including post-silicon data analysis and ATE firmware considerations.