MTS, DDR Design Verification (AI2487)

SiMa Technologies, Inc.; San Jose (CA); Hybrid; USD 176,000 - 282,000; Full time

Benefits offered by this job

Private company equity

Job summary

SiMa Technologies, Inc. is seeking a DDR Design Verification Engineer to define and develop verification methodologies for the MLSoC DDR block.

You will create DDR test plans, test benches, and test cases, driving verification across LPDDR IP and DDR-IO interfaces in a collaborative lab setting. You will work with Architecture, RTL/uArch, and cross-functional teams to verify functionality, performance, and coverage, with the opportunity to contribute to DDR bring-up on silicon in our San Jose

Qualifications

• 10+ years in SoC design verification or 8+ years with MS in CS/EE.
• Proficient in SystemVerilog, UVM, constrained random, coverage-driven verification.
• DDR/LPDDR IP verification and DDR-IO verification experience required; LPDDR5 knowledge preferred.

Responsibilities

• Develop DDR verification methodology, test plans, benches, and test cases.
• Execute plans to verify MLSoC DDR functionality, performance, and coverage.
• Collaborate with Architecture, RTL/uArch, and cross-functional teams; bring-up on silicon.

Skills

SystemVerilog

UVM

Constrained random

Coverage driven verification

DDR/LPDDR IP verification

Python/Perl scripting

Test bench development

Debugging

Education

BS in CS/EE

MS in CS/EE

Job description

Job Title: MTS, DDR Design Verification

Job Location:San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office)

Job ID: AI2487

Job Description:

As the DDR Design Verification Engineer, you will participate in definition and develop the verification methodology for SiMa.ai’s MLSoC™. You will be responsible for developing DDR test plans, test-benches (drivers, monitors and checkers/scoreboard etc..) and test cases. You will be executing test plans to verify the MLSoC - DDR functionality, performance and coverage analysis. You will work closely with the Architecture, RTL/uArch, and cross-functional teams. Opportunity to participate on DDR bring up on MLSoC Silicon in the lab.

Required Background:

• BS in Computer Science/EE with 10+ years of experience or MS in computer science/EE with 8+ years of experience in SoC design verification.
• Experience with block level, cluster level or chip/SoC level verification.
• Proficiency in system verilog, UVM, constrained random and coverage driven verification methodology.
• DDR controller and/or DDR-IO verification experience is a must.
• Very good understanding of LPDDR JDEC specifications preferably for LPDDR5.
• Good understanding of DDR controller and phy functionality.
• Experience with development of test bench components, test plans for DDR/LPDDR IP verification.
• Good system verilog programming, debug and problem solving skills.
• Scripting languages, python or perl is a plus.

Personal attributes:

Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and ishighly accountable. Good communication skills.

Salary and Benefits:

The annual salary for this position ranges from $176,200 to $281,900. The actual annual salary offered will depend on several factors, including - among others - job-related skills, experience, technical expertise, qualifications, work location, and business needs. The annual salary range for this position is subject to change and may be adjusted in the future.

In addition to base salary, this role is also eligible for private company equity, and a comprehensive package of employee benefits. Please note that the salary ranges listed for U.S. roles reflect base salary only and do not include equity or other forms of compensation.

EEO Employer:

SiMa is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.