Data Center SoC Power & Limits Architect

Qualcomm; San Diego (CA); Sur place; USD 164 000 - 246 000; Plein temps

Avantages offerts par ce poste

Competitive annual discretionary bonus

RSU grants

Comprehensive benefits package

Résumé du poste

Qualcomm is seeking a Data Center Power & Limits Architect in San Diego, California. This role focuses on defining and driving power management architecture for large-scale compute platforms. The successful candidate will have over 10 years of experience and will be responsible for optimizing thermal and electrical limits across systems.

The position offers a competitive salary between $164,000 and $246,000, along with a comprehensive benefits package and bonus opportunities.

Qualifications

• 10+ years of experience in power architecture or related domains.
• Experience with power management systems and control.
• Understanding of telemetry and system monitoring.

Responsabilités

• Define and drive power management architecture for compute platforms.
• Architect dynamic power control systems.
• Develop system-level models to predict performance.

Connaissances

Power management systems

Thermal and electrical constraints

Data center/server architecture

Modeling and analysis tools

Formation

Bachelor’s degree in Science, Engineering, or related field

Master’s or PhD with relevant experience

Outils

MATLAB

Python

Description du poste

Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

The Data Center Power & Limits Architect will define and drive next-generation power management, thermal, and system limits architecture for large-scale compute platforms (SOC, servers, racks, and cluster-level deployments).

With AI/HPC workloads pushing infrastructure to electrical and thermal limits, this role is responsible for enabling maximum sustained performance within constrained power, cooling, and reliability envelopes by architecting end-to-end power and limits systems across silicon, platform, and data center infrastructure.

Key Responsibilities

1. Power & Limits Architecture Definition
   • Define holistic power, thermal, and electrical limits architecture across silicon, board, system, rack, and cluster levels
   • Architect power budgeting, allocation, and enforcement mechanisms across CPU, GPU, memory, accelerators, and I/O
   • Develop strategies to maximize performance under datacenter-level constraints (rack power caps, cooling limits, PUE targets)
2. Dynamic Control & Optimization
   • Architect advanced dynamic power control systems (e.g., DVFS/DCVS, AVS-like systems) for fast transient response
   • Design closed-loop control systems using telemetry and feedback to optimize performance vs. constraints
   • Develop proactive and reactive limit management (thermal throttling, power capping, workload shaping)
3. Telemetry & System Integration
   • Define requirements and interfaces for telemetry infrastructure (sensors, BMC, firmware, system SW)
   • Enable real-time monitoring and decision making across system layers
   • Ensure integration with platform controllers (e.g., BMC/EC, rack management, orchestration layers)
4. Cross-Layer Co-Design
   • Collaborate with:
     • Silicon/SoC architects (power islands, regulators, sensors)
     • Platform teams (VRs, PDN, cooling)
     • Software/firmware teams (power management algorithms)
     • Data center infrastructure teams (rack-level optimization)
   • Define hardware/software partitioning for limits enforcement with minimal overhead
5. Modeling, Simulation & Validation
   • Develop system-level models (MATLAB/Simulink, architectural simulators) to:
     • Predict performance vs. power/thermal constraints
     • Evaluate algorithms and architecture trade-offs
   • Perform workload-driven analysis to validate architecture decisions
6. Innovation & Future Architecture
   • Drive innovations in:
     • Power delivery efficiency
     • Thermal-aware scheduling
     • AI workload-aware limits
     • Rack/cluster-level power orchestration
   • Define next-generation architectures to support scaling AI/HPC performance under constrained infrastructure

Required Qualifications

• 10+ years of experience in power architecture, system architecture, or related domains
• Deep expertise in:
  • Power management systems and limits control
  • Thermal and electrical constraints in high-performance systems
  • DVFS/DCVS, power capping, and control systems
• Strong understanding of:
  • Data center/server architecture (CPU/GPU/accelerators, memory systems)
  • Power delivery networks (VRs, PDN, rack power distribution)
  • Telemetry, sensors, and system monitoring
• Experience with modeling and analysis tools (e.g., MATLAB, Python)

Minimum Qualifications

• Bachelor’s degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• Master’s degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Pay Range and Other Compensation & Benefits

$164,000.00 - $246,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.