Dallas RTL Design Engineer - High-Speed IP/Verilog

Talent 101, Inc; Dallas (TX); Sur place; USD 120 000 - 160 000; Plein temps

Résumé du poste

Talent 101, Inc in Dallas seeks a Digital Design Engineer (RTL) with IP development experience. You will architect synthesizable RTL in Verilog for high-speed IO and Ethernet MAC/PHY, and integrate third-party IPs into SoC environments.

You will collaborate with system architects and verification teams to ensure robust RTL and timely tape-out. Ideal candidates have 7+ years in digital design, strong Verilog/SystemVerilog skills, and hands-on experience with Synopsys IPs and Design Compiler,

Qualifications

• 7+ years of digital design experience in complex high-speed IO.
• Strong knowledge of Verilog (SystemVerilog optional) for synthesizable RTL.
• Experience in custom IP development and modifying Synopsys DesignWare IPs.
• Familiarity with IP-XACT and SoC integration flows.
• Experience with PCIe, USB, DDR, Ethernet protocols.

Responsabilités

• Architect RTL in Verilog for high-speed IO subsystems and Ethernet MAC/PHY.
• Develop and modify Synopsys DesignWare IPs to meet targets.
• Ensure RTL meets specs and protocol standards (IEEE 802.3).
• Integrate third-party IPs into SoC environments and customize interfaces.
• Collaborate with system architects to align IP with system goals.
• Work with verification teams to define tests and debug RTL.

Connaissances

Verilog

SystemVerilog

High-speed interfaces

PCIe

USB

Ethernet

Clock domain crossing

IP integration

Outils

Synopsys Design Compiler

PrimeTime

SpyGlass

Conformal

Description du poste

Talent 101, Inc in Dallas seeks a Digital Design Engineer (RTL) with IP development experience. You will architect synthesizable RTL in Verilog for high-speed IO and Ethernet MAC/PHY, and integrate third-party IPs into SoC environments.

You will collaborate with system architects and verification teams to ensure robust RTL and timely tape-out. Ideal candidates have 7+ years in digital design, strong Verilog/SystemVerilog skills, and hands-on experience with Synopsys IPs and Design Compiler,