CPU Verification Engineer: Validate Next-Gen Silicon

Intel Corporation; Hillsboro (OR); On-site; USD 106,000 - 200,000; Full time

Job summary

Intel Corporation in Austin, Texas seeks a CPU verification engineer to drive functional correctness of CPU logic through pre-silicon verification methodologies.

You will develop verification plans, build UVM-based testbenches, run system simulations, and collaborate with CPU architects and RTL designers to verify complex architectural features. The role requires a STEM degree and 1+ year experience with SystemVerilog/UVM, Python or Perl, and C++; on-site work is required.

Qualifications

• Bachelor’s or Master’s degree in EE/CE/STEM with 1+ years of relevant experience.
• 1+ years of SystemVerilog in UVM-based testbenches for reusable verification environments.
• 1+ years of scripting with Python or Perl and C++.

Responsibilities

• Develop and execute comprehensive verification plans to validate CPU logic against architectural specifications.
• Build scalable UVM-based testbenches and define robust functional coverage models.
• Run system-level simulations to uncover design bugs and ensure functional integrity.
• Debug and root-cause issues in the pre-silicon environment; implement corrective actions to resolve test failures.
• Collaborate closely with CPU architects and RTL designers to verify complex features.
• Document verification strategies and lead technical reviews with design and architecture teams.
• Maintain and enhance verification infrastructure and methodologies.
• Contribute to the definition and refinement of CPU architecture and microarchitecture features.

Skills

SystemVerilog

UVM

Python

C++

Education

Bachelor’s Degree in Electrical/Electronics or Computer Engineering or STEM

Master’s Degree in Electrical/Electronics or Computer Engineering or STEM

Tools

Synopsys simulators

GIT

x86 assembly

Job description

Intel Corporation in Austin, Texas seeks a CPU verification engineer to drive functional correctness of CPU logic through pre-silicon verification methodologies.

You will develop verification plans, build UVM-based testbenches, run system simulations, and collaborate with CPU architects and RTL designers to verify complex architectural features. The role requires a STEM degree and 1+ year experience with SystemVerilog/UVM, Python or Perl, and C++; on-site work is required.