CPU Timing Engineer - Drive Closure & Flow Optimization

Apple Inc.; Santa Clara (CA); On-site; USD 150,400 - 277,600; Full time

Benefits offered by this job

Stock options / RSUs

Discounted Apple products

Tuition reimbursement

Relocation assistance

Comprehensive medical and dental cover

Job summary

Apple Inc. in Santa Clara, California, is seeking a CPU Design Timing Engineer to own the timing closure of the project.

You will work with the CAD team to develop the timing flow, including scripting to improve analysis flows and engineer efficiency, and collaborate with CPU micro-architects to drive timing closure. The role requires a BS with 3+ years of relevant experience, plus hands-on use of static timing analysis, noise analysis, and variation modeling.

Qualifications

• Minimum BS and 3+ years of relevant experience.
• Experience with static timing analysis, noise analysis, and fixing noise in designs.
• Experience with variation modeling.
• Experience with TCL and either Perl or Python.

Responsibilities

• Own timing closure of the CPU design project.
• Collaborate with CAD team to develop timing flow and scripting to improve analysis flows and engineer efficiency.
• Work with CPU micro-architects and implementation engineers to drive timing closure for the CPU.

Skills

Static timing analysis

Noise analysis

Variation modeling

TCL

Python

Perl

Education

Bachelor's degree (BS)

Tools

PrimeTime

Tempus

Job description

Apple Inc. in Santa Clara, California, is seeking a CPU Design Timing Engineer to own the timing closure of the project.

You will work with the CAD team to develop the timing flow, including scripting to improve analysis flows and engineer efficiency, and collaborate with CPU micro-architects to drive timing closure. The role requires a BS with 3+ years of relevant experience, plus hands-on use of static timing analysis, noise analysis, and variation modeling.