CAD Timing Engineer - Gate-Level Flows & Methodologies

Apple Inc.; San Jose (CA); On-site; USD 140,000 - 180,000; Full time

Job summary

Apple Inc. is seeking a CAD Engineer focused on Timing for Gate-Level Flows & Methodologies in San Jose, CA. You will contribute to timing analysis, create and refine flows, and partner with design teams to drive first-time silicon success.

In this role you will develop and maintain gate-level STA flows, debug issues related to constraints and scripts, and work with EDA vendors to adopt new capabilities for performance and productivity gains. A BS degree and 3 years’ experience are required.

Qualifications

• BS degree and 3 years of relevant industry experience.
• Experience with static timing analysis tools and flows.
• Familiar with Python and Tcl or similar high-level languages.
• Knowledge of timing constraints and STA of large high-performance SoCs.
• Good communicator capable of cross-team collaboration.

Responsibilities

• Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs.
• Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure.
• Facilitate and drive STA methodology changes to improve STA flows, efficiency, productivity, and silicon timing correlation.
• Develop and maintain scripts and methods for timing analysis and power reduction.
• Develop and support methodologies, tools, and flows used in timing constraint verification, driving best practices across design teams.
• Analyze timing paths to identify key issues, including post-silicon timing debug.
• Collaborate with EDA vendors to incorporate new capabilities to solve technical problems.

Skills

Static timing analysis

Python

Tcl

SoC timing

Noise & Crosstalk

Education

BS degree

Tools

Flow scripting

EDA tools

Job description

Apple Inc. is seeking a CAD Engineer focused on Timing for Gate-Level Flows & Methodologies in San Jose, CA. You will contribute to timing analysis, create and refine flows, and partner with design teams to drive first-time silicon success.

In this role you will develop and maintain gate-level STA flows, debug issues related to constraints and scripts, and work with EDA vendors to adopt new capabilities for performance and productivity gains. A BS degree and 3 years’ experience are required.