CPU Power & Clock Management Verification Engineer

Apple Inc.; California (MO); On-site; USD 120,000 - 180,000; Full time

Job summary

Apple is seeking a Processor Power Management Verification Engineer to join our processor verification team. You will work closely with architecture and RTL designers, develop test plans, and drive verification of Power Management and Clock Control logic across simulation and emulation environments.

The role emphasizes test development in SystemVerilog, assertions, formal verification, and coverage analysis.

Qualifications

• Experience with digital logic, micro-processor architecture, or power management architecture.
• Experience with digital design verification including knowledge of Verilog/System-Verilog based testbenches, transactors checkers.

Responsibilities

• Work closely with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic
• Develop and execute test plans and schedules for the power management and clock control logic
• Develop tests in Assembly, Scripts, System Verilog, or vectors according to test plans to drive testing in simulation and emulation environments
• Root cause failures and propose potential solution to the design team
• Work with silicon bringup team on developing tests that work in the emulation and FPGA environments. Aid silicon debug in related part of the design
• Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered
• Develop checkers or Verilog/System Verilog-base transactor to verify the design
• Write assertions and apply formal verification to the design

Skills

Digital logic

Micro-processor architecture

Power management architecture

Tools

Verilog/SystemVerilog

Job description

Apple is seeking a Processor Power Management Verification Engineer to join our processor verification team. You will work closely with architecture and RTL designers, develop test plans, and drive verification of Power Management and Clock Control logic across simulation and emulation environments.

The role emphasizes test development in SystemVerilog, assertions, formal verification, and coverage analysis.