CPU Power Management Verification Engineer

Socket.dev; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Apple in Austin, TX is seeking a Processor Power Management Verification Engineer to join the center of a chip design effort with broad collaboration across architecture and RTL teams.

You will verify power management and clock control logic, develop tests in SystemVerilog, assemble test plans, and drive coverage and silicon bring-up in emulation and FPGA environments. You will mentor junior engineers and contribute to robust verification methodologies.

Qualifications

• BS is required.
• Experience with digital logic, microprocessor and power management architecture.
• Knowledge of Verilog/SystemVerilog based testbenches, transactors and checkers.
• Programming skills in Perl or Python.

Responsibilities

• Verify the functionality of Power Management and Clock Control logic.
• Develop and execute test plans for power management and clock control.
• Write tests in Assembly, Scripts, SystemVerilog, or vectors for simulating environments.
• Identify root causes and propose design fixes.
• Collaborate with silicon bring-up on emulation/FPGA tests and debugging.
• Develop coverage monitors and ensure test coverage of plans.
• Create checkers or transactors and apply assertions and formal verification.

Skills

Digital logic

Micro-processor architecture

Power management architecture

Verilog/SystemVerilog testbenches

Transactors / checkers

Perl

Python

UVM

Education

BS in Electrical/Computer Engineering

Master’s degree preferred

Job description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be at the center of a chip design effort collaborating with many teams, with a critical impact on getting functional products to millions of customers quickly. We are looking for a strong candidate to join our processor verification team focusing on Power Management and Clock Control verification.

Description

As a Processor Power Management Verification Engineer, you will have the responsibilities as follows:

• Work closely with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic
• Develop and execute test plans and schedules for the power management and clock control logic
• Develop tests in Assembly, Scripts, System Verilog, or vectors according to test plans to drive testing in simulation and emulation environments
• Root cause failures and propose potential solution to the design team
• Work with silicon bringup team on developing tests that work in the emulation and FPGA environments. Aid silicon debug in related part of the design
• Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered
• Develop checkers or Verilog/System Verilog-base transactor to verify the design
• Write assertions and apply formal verification to the design

Minimum Qualifications

• Minimum BS
• Experience with digital logic, micro-processor architecture, or power management architecture
• Experience with digital design verification including knowledge of Verilog/System-Verilog based testbenches, transactors checkers
• Programming skills include scripting languages such as Perl or Python

Preferred Qualifications

• Master’s degree preferred
• Experience in processor or power management architecture and verification
• In-depth knowledge in design verification environments like random constraint verification and/or UVM base testbenches
• Experience in system Verilog assertions or silicon bringup or UPF and low power simulation
• Experience with advanced verification techniques such as formal verification is a plus
• Advanced programming skills such as object orientated programming or CPU assembly language is a plus
• Should be an extraordinary teammate with excellent communication skills with the ability to articulate complex design issues during verification effort
• Be able to create and follow detailed work schedules and work independently on the verification efforts for a block/area of the design