Physical Design (Multiple levels)

Qualcomm; San Diego (CA); On-site; USD 116,000 - 173,000; Full time

Job summary

Qualcomm Technologies, Inc. in San Diego, CA, seeks a skilled Physical Design engineer to drive all stages of the ASIC/SoC design flow from netlist to tape-out. You will develop physical design solutions for high-speed, low-power ICs and collaborate with multiple teams to ensure successful sign-off.

The role requires 2–10+ years in Physical Design, experience with Cadence Innovus and Synopsys tools, and a strong background in timing, SI, and RTL/DFT collaboration.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 2-10+ years of industry experience or relevant academic/project experience in Physical Design.
• Experience with Cadence Innovus and/or Synopsys Fusion Compiler.
• Experience with Static Timing Analysis and timing closure using Synopsys PrimeTime SI.
• DFT-aware physical implementation and constraint management.

Responsibilities

• Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
• Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
• Perform floorplanning, partitioning, power planning, and IR-drop analysis.
• Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across MMMC scenarios.
• Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
• Perform RC extraction, physical verification, and formal verification activities.
• Implement ECOs and support design convergence through sign-off.
• Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure project success.
• Contribute to low-power implementation methodologies and customized place-and-route solutions.
• Develop automation and productivity tools using scripting languages and software development techniques.

Skills

Strong problem solving

ASIC development/debugging

Education

Bachelor's or Master's degree in Electrical/Computer Engineering/Computer Science

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PrimeTime SI

Job description

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drive communication and data processing transformation, helping create a smarter, more connected future for all.

Key Responsibilities

• Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
• Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
• Perform floorplanning, partitioning, power planning, and IR-drop analysis.
• Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios.
• Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
• Perform RC extraction, physical verification, and formal verification activities.
• Implement engineering change orders (ECOs) and support design convergence through sign-off.
• Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution.
• Contribute to the development of innovative low-power implementation methodologies and customized place-and-route solutions.
• Develop automation and productivity tools using scripting languages and software development techniques.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 2-10+ years of industry experience or relevant academic/project experience in Physical Design.

Preferred Qualifications

• Experience in one or more of the following areas:
  • ASIC/SoC Physical Design implementation.
  • Place and Route using Cadence Innovus and/or Synopsys Fusion Compiler.
  • Static Timing Analysis and timing closure using Synopsys PrimeTime SI.
  • Physical verification and design sign-off methodologies.
  • Formal verification techniques and tools.
  • Power domain implementation and low-power design methodologies.
  • Clock Tree Synthesis (CTS), routing, and timing optimization.
  • Low power implementation techniques experience
  • Signal integrity, noise analysis, and MMMC sign-off flows.
  • DFT-aware physical implementation and constraint management.
  • Programming and automation using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments.
  • Perl/Tcl, Python skills are needed.
  • Strong problem solving and ASIC development/debugging skills.

Qualcomm is an equal opportunity employer.

If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process.

You may e-mail [e-mail] or call Qualcomm's toll-free number found here.

Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.

Qualcomm is also committed to making our workplace accessible for individuals with disabilities.

(Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities.

We will not respond here to requests for updates on applications or resume inquiries).

EEO Employer

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range and Other Compensation & Benefits:

$115,600.00 - $173,400.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer and you can review more details about our US benefits at this link.