Staff SWE, ML Compiler Performance Engineer Co-Design

Google; Mountain View (CA); On-site; USD 207,000 - 300,000; Full time

Job summary

Google in Mountain View seeks a senior software engineer to advance TPU, ML workloads, and high-performance systems. You will design, test, and deploy software across large-scale data analysis, performance optimization, and compiler integration.

The role requires strong C++/Python, 8+ years of experience, and the ability to lead complex initiatives across teams. You will contribute to open-source model mappings and TPU performance strategies.

Qualifications

• Bachelor's degree or equivalent practical experience.
• 8 years of experience programming in C++ or Python.
• 5 years of experience testing, and launching software products.
• 5 years of experience with performance, large-scale systems data analysis, visualization tools, or debugging.
• 3 years of experience with software design and architecture.

Responsibilities

• Deliver certified performance benchmarks six months pre-pilot as primary targets for pricing, capacity planning, and kernel optimization.
• Adapt emerging open-source models into TPU-native paired variants, including sparsity optimization, to demonstrate differentiated TPU performance.
• Ingest and optimize multi-turn agentic workflows, reasoning loops, and prompt and decode topologies prior to silicon tape-out.
• Author robust reference implementations using PyTorch, JAX, or Pallas that meet pre-pilot goals under compiler constraints.
• Partner with director and executive technical leadership across TPU Hardware, XLA Compiler, and Cloud AI Systems to steer multi-year roadmaps.

Skills

C++

Python

Testing

Performance analysis

Software design

Education

Bachelor's degree or equivalent pr.

Tools

MLIR

XLA

JAX

PyTorch

Pallas

Triton

CUDA

Job description

Minimum qualifications:

• Bachelor's degree or equivalent practical experience.
• 8 years of experience programming in C++ or Python.
• 5 years of experience testing, and launching software products.
• 5 years of experience with performance, large-scale systems data analysis, visualization tools, or debugging.
• 3 years of experience with software design and architecture.

Preferred qualifications:

• Deep technical proficiency ML workload performance modeling on pre-silicon systems, familiarity with high level compiler intermediate representations (e.g., MLIR dialects, XLA, HLO), ML execution frameworks (JAX, PyTorch, PyTorch/XLA), or accelerator kernel programming (Pallas, Triton, CUDA).
• Demonstrated track record of architecting, validating, or extending high-performance simulation tools, emulation frameworks, or analytical performance modeling pipelines (e.g., roofline models, cycle-accurate or compiler-aware simulators).
• Proven L6-level ability to lead complex, multi-quarter technical initiatives across distinct organizational boundaries (e.g., hardware design, compilers, AI research, and cloud infrastructure).

About the job

Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google’s needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward.

With your technical expertise you will manage project priorities, deadlines, and deliverables. You will design, develop, test, deploy, maintain, and enhance software solutions.

The MARC (Model Architecture and Realizable-performance Co-design) team is Google’s proactive, ahead-of-silicon co-design engine. We operate at the critical intersection of frontier ML workloads and multi-year TPU silicon roadmaps. Given rapid 6-month model breakthroughs and complex Compound AI Systems, our mandate is to focus on the 12+ month time window between Hardware Architecture Freeze and Physical Silicon Pilot.

In this role, you will define and own the strategy for enabling open-source ML models to achieve TPU performance with internal models at launch. You will establish a principled, scalable methodology to analyze mapping gaps across open-source model families.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $207000 - $300000 (USD) + 20% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Deliver certified performance benchmarks six months pre-pilot as primary targets for pricing, capacity planning, and kernel optimization.
• Adapt emerging open-source models into TPU-native paired variants, including sparsity optimization, to demonstrate differentiated TPU performance.
• Ingest and optimize multi-turn agentic workflows, reasoning loops, and prompt and decode topologies prior to silicon tape-out.
• Author robust reference implementations using PyTorch, JAX, or Pallas that meet pre-pilot goals under compiler constraints.
• Partner with director and executive technical leadership across TPU Hardware, XLA Compiler, and Cloud AI Systems to steer multi-year roadmaps.

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