CPU Memory Design Engineer - High-Performance, Low-Power

Intel; Austin (TX); Hybrid; USD 142,000 - 200,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel's CPU Memory Design Engineer in Austin, TX, will shape high-performance memory solutions for CPUs and SoCs. You will design, simulate, and optimize SRAMs, caches, and memory cores, collaborating with architects and validation teams to improve power, performance, and density.

The role emphasizes fast execution, memory pathfinding, and innovative circuit techniques, with a strong focus on low-power and area efficiency. This is a hybrid role within a leading semiconductor environment at Intel.

Qualifications

• CMOS circuit design, digital logic optimizations and trade-offs for power, performance and area.
• Experience in VLSI circuits and design methodologies.
• Memory design experience and low-power techniques.
• Knowledge of design tools and flow methodologies for silicon integration.

Responsibilities

• Memory circuit design, characterization and simulations.
• Cache design and periphery IP development for PPA goals.
• Memory bit-cell and array/IP design with optimization.
• Execute project schedules and define methodologies.

Skills

CMOS design

VLSI design

Memory design

Low-power techniques

Circuit optimization

PPA optimization

Education

Bachelor's degree in Electrical / Computer Engineering or STEM field

Master's degree in Electrical / Computer Engineering or STEM field

PhD in Electrical / Computer Engineering or STEM field

Tools

EBB design tools

Job description

Intel's CPU Memory Design Engineer in Austin, TX, will shape high-performance memory solutions for CPUs and SoCs. You will design, simulate, and optimize SRAMs, caches, and memory cores, collaborating with architects and validation teams to improve power, performance, and density.

The role emphasizes fast execution, memory pathfinding, and innovative circuit techniques, with a strong focus on low-power and area efficiency. This is a hybrid role within a leading semiconductor environment at Intel.