CPU Circuit Design Engineer: Power, Performance & Memory

Intel; Austin (TX); On-site; USD 91,000 - 173,000; Full time

Job summary

Intel is seeking a College Grad engineer to design, develop, and build custom digital circuits for a CPU, including memory and caches. You will work on floorplans, circuit design, schematic entry, simulation, and verification to optimize power, performance, area, and yield.

Collaborate with CPU architecture and layout teams, develop DFT models, memory test tools, and automation to streamline design flows while meeting robustness and electrical requirements.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or STEM field.
• 1+ years of CMOS circuit design and memory design experience.
• Experience in digital logic design and power-performance-area trade-offs.

Responsibilities

• Designs, develops, and builds custom digital circuits for a CPU, including memory and caches.
• Designs floorplans, performs circuit design, schematic entry, simulation for CPU blocks, and verifies functionality to optimize for power, performance, area and yield.
• Creates block level DFT models, develops memory test tools, and improves and automates flows and methodologies to streamline design.
• Collaborates cross functionally to report design progress and to collect, track, and resolve any performance and CPU design issues.
• Optimizes performance, power, and area, reduces leakage, and drives characterization of memory instances and memory compilers.
• Works with CPU architecture and layout teams to design circuit for best functionality, robustness, and electrical capabilities.

Skills

CMOS circuits design

Digital logic

Power-Performance-Area trade-offs

Memory design experience

Education

Bachelor's degree in Electrical Engineering or Computer Engineering or STEM

Job description

Intel is seeking a College Grad engineer to design, develop, and build custom digital circuits for a CPU, including memory and caches. You will work on floorplans, circuit design, schematic entry, simulation, and verification to optimize power, performance, area, and yield.

Collaborate with CPU architecture and layout teams, develop DFT models, memory test tools, and automation to streamline design flows while meeting robustness and electrical requirements.