CPU Frontend RTL Design Engineer with Equity & Bonus

Google LLC

Austin (TX)

On-site

USD 138,000 - 197,000

Full time

8 hours ago
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Benefits offered by this job

Bonus target
Equity
Benefits

Job summary

Google LLC is seeking a CPU frontend designer to help push the boundaries of custom silicon for flagship products. You will drive microarchitectural decisions and RTL design for a next‑generation CPU while partnering with architects, verification, and physical design teams to balance power, performance, and area.

Ideal candidates bring strong digital logic background, Verilog/SystemVerilog fluency, and microprocessor architecture experience. In-person interviews are common.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Science or related field or equivalent practical experience.
  • 4 years of experience with digital logic design principles, RTL design concepts, and Verilog/SystemVerilog.
  • Experience with microprocessor architecture.

Responsibilities

  • Contribute to CPU frontend design with focus on microarchitecture and RTL.
  • Propose features for improved performance with trade-off studies and data-driven decisions.
  • Deliver designs meeting power, performance and area goals with production quality.
  • Collaborate with verification and physical design teams to ensure design success.
  • Support performance modeling efforts and guidance to the team.

Skills

Digital logic design
RTL design
Verilog
SystemVerilog
Microprocessor architecture

Education

Bachelor's degree (Electrical Engineering, CS or related)
Master’s degree or PhD (preferred)

Tools

C++
Python

Job description

Google LLC is seeking a CPU frontend designer to help push the boundaries of custom silicon for flagship products. You will drive microarchitectural decisions and RTL design for a next‑generation CPU while partnering with architects, verification, and physical design teams to balance power, performance, and area.

Ideal candidates bring strong digital logic background, Verilog/SystemVerilog fluency, and microprocessor architecture experience. In-person interviews are common.

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