Senior CPU RTL Engineer - Microarchitecture & Frontend

Google LLC; Portland (OR); On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Equity

Bonus plan

Benefits

Job summary

Google LLC is seeking a senior CPU/AI accelerator designer to join a team that builds custom silicon powering its direct-to-consumer products. You will contribute to microarchitecture, RTL design, and performance optimizations to deliver industry-leading efficiency.

The role requires strong SystemVerilog skills, ARM ISA experience, and a track record in SOC integration, collaborating with software, architecture, and verification teams. Equity and a 20% bonus target are part of the compensation.

Qualifications

• Bachelor's degree in EE/CE/CS or equivalent experience.
• 8 years of RTL/CPU/AI accelerator design experience.
• Experience with SystemVerilog and related design processes (Lint, UPF).

Responsibilities

• Develop CPU subsystem front-end designs with emphasis on microarchitecture and RTL.
• Propose microarchitecture features and collaborate on trade-off studies.
• Communicate design trade-offs and deliver production-quality designs meeting PPA goals.
• Collaborate with Verification, Physical Design and Power teams to meet freq/power/area goals.
• Apply modern techniques to guide performance evaluation and design constructs.

Skills

8+ years RTL design experience

SystemVerilog

Front-end CPU design

ARM ISA experience

SOC design experience

Power/Performance/Area optimization

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (or related field) or equivalent experience

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science

Job description

Google LLC is seeking a senior CPU/AI accelerator designer to join a team that builds custom silicon powering its direct-to-consumer products. You will contribute to microarchitecture, RTL design, and performance optimizations to deliver industry-leading efficiency.

The role requires strong SystemVerilog skills, ARM ISA experience, and a track record in SOC integration, collaborating with software, architecture, and verification teams. Equity and a 20% bonus target are part of the compensation.