CPU RTL Design Engineer

Google LLC; Austin (TX); On-site; USD 138,000 - 197,000; Full time

Benefits offered by this job

Bonus target

Equity

Benefits

Job summary

Google LLC is seeking a CPU frontend designer to help push the boundaries of custom silicon for flagship products. You will drive microarchitectural decisions and RTL design for a next‑generation CPU while partnering with architects, verification, and physical design teams to balance power, performance, and area.

Ideal candidates bring strong digital logic background, Verilog/SystemVerilog fluency, and microprocessor architecture experience. In-person interviews are common.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science or related field or equivalent practical experience.
• 4 years of experience with digital logic design principles, RTL design concepts, and Verilog/SystemVerilog.
• Experience with microprocessor architecture.

Responsibilities

• Contribute to CPU frontend design with focus on microarchitecture and RTL.
• Propose features for improved performance with trade-off studies and data-driven decisions.
• Deliver designs meeting power, performance and area goals with production quality.
• Collaborate with verification and physical design teams to ensure design success.
• Support performance modeling efforts and guidance to the team.

Skills

Digital logic design

RTL design

Verilog

SystemVerilog

Microprocessor architecture

Education

Bachelor's degree (Electrical Engineering, CS or related)

Master’s degree or PhD (preferred)

Tools

C++

Python

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; Austin, TX, USA; Portland, OR, USA.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with microprocessor architecture.

Preferred qualifications:

• Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
• Experience with modern processor microarchitecture and related technologies and algorithms, through academic projects or industry experience.
• Knowledge of programming languages such as C, C++, and Python.
• Knowledge of general purpose operating systems such as Linux or Android.
• Knowledge of how to leverage AI to offload tasks to maximize productivity.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google .

• Contribute to CPU frontend design, emphasizing on microarchitecture and RTL design for a next generation CPU.
• Propose performance enhancing microarchitecture features with efficiency in mind. Work with architects and performance teams for trade-off studies. Communicate pros and cons of microarchitecture proposals. Facilitate final decision making by gathering necessary data and present to the larger team.
• Deliver desi gns meeting power, performance and area (PPA) goals with production quality. Become familiar with state-of-the-art techniques for memory subsystem design.
• Leverage design understanding in order to provide guidance to, and participation in, the performance modeling effort.
• Work cl osely with the functional verification team to ensure production quality designs, and with the physical design team to meet frequency, power, and area goals.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .