CPU Emulation Engineer, Silicon

Socket.dev; Austin (TX); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Bonus target 15%

Equity and benefits

Job summary

Google is seeking a senior RTL engineer to join a team developing custom silicon solutions powering the company\'s direct-to-consumer products. You\'ll contribute to advanced emulation and FPGA prototyping efforts across industry-standard platforms, shaping performance and efficiency.

You will architect RTL partitions, drive pre-silicon verification, and collaborate with DV and silicon design teams to deliver scalable hardware solutions.

Qualifications

• Bachelor's degree or equivalent practical experience in a relevant field.
• 8+ years of experience with industry-standard emulation or FPGA prototyping platforms.
• Experience with RTL design using Verilog or SystemVerilog.
• Experience scripting or developing automation workflows in Python, Perl, TCL, or Makefiles.

Responsibilities

• Architect and drive RTL partitioning, FPGA synthesis, and validation strategies for emulation platforms.
• Define and execute test suites, benchmarks, and workloads for pre-silicon verification and system-level validation.
• Lead debugging methodologies to rapidly isolate and resolve complex functional failures in large-scale designs.
• Optimize model compile times, improve FPGA routing efficiency, and maximize hardware resource utilization in emulation farms.
• Architect automation workflows using modern scripting languages and collaborate with IP design and verification stakeholders to streamline CI.

Skills

RTL design Verilog/SystemVerilog

Automation scripting

Emulation/FPGA prototyping

Education

Bachelor's degree in EE/CE/CS or related field

Tools

Industry-standard emulation platforms

Job description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with industry-standard emulation or FPGA prototyping platforms (e.g., Synopsys ZeBu/HAPS, Cadence Palladium/Protium, Siemens Veloce).
• Experience in RTL design using Verilog or SystemVerilog.
• Experience writing scripts or developing automation workflows in Python, Perl, TCL, or Makefiles.

Preferred qualifications:

• Experience scaling compilation and routing across multi-FPGA and enterprise emulation platforms.
• Experience verifying and troubleshooting complex semiconductor IP blocks.
• Experience collaborating with cross-functional design verification (DV) and silicon design teams.

About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities:

• Architect and drive advanced Register-Transfer Level (RTL) partitioning, Field-Programmable Gate Array (FPGA) synthesis, and validation strategies for industry-standard emulation platforms such as Synopsys ZeBu, Cadence Palladium, or Siemens Veloce.
• Define and execute comprehensive test suites, complex performance benchmarks, and software workloads to ensure pre-silicon verification and system-level validation.
• Guide advanced debugging methodologies to rapidly isolate and resolve complex functional failures within multi-million gate subsystem designs and full-chip environments.
• Lead initiatives to optimize model compile times, improve FPGA routing efficiency, and maximize hardware resource utilization across enterprise emulation farms.
• Architect custom automation workflows using modern scripting languages and collaborate with IP design and verification stakeholders to streamline continuous integration.