CPU Emulation Engineer, Silicon

Google; City of Poughkeepsie (NY); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is hiring for a role in which you will architect RTL partitioning, FPGA synthesis, and validation strategies across industry-standard emulation platforms. You will define comprehensive test suites and workloads for pre-silicon verification, guiding debugging to resolve complex failures in multi-million gate designs.

Your work will optimize compile times, routing efficiency, and hardware resource utilization across enterprise emulation farms while coordinating automation workflows with IP

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with industry-standard emulation or FPGA prototyping platforms (e.g., ZeBu/HAPS, Palladium/Protium, Veloce).
• Experience in RTL design using Verilog or SystemVerilog.
• Experience writing scripts or developing automation workflows in Python, Perl, TCL, or Makefiles.

Responsibilities

• Architect RTL partitioning and FPGA synthesis for emulation platforms.
• Define test suites, benchmarks, and workloads for pre-silicon verification.
• Lead debugging to resolve complex multi-million gate design issues.
• Optimize model compile times and FPGA routing across emulation farms.
• Architect automation workflows and collaborate with IP/design teams.

Skills

RTL design

Verilog/SystemVerilog

Python scripting

Automation workflows

Education

Bachelor's degree in EE/CE/CS

Tools

Synopsys ZeBu

Cadence Palladium/Protium

Siemens Veloce

Job description

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA; Portland, OR, USA; Poughkeepsie, NY, USA.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with industry-standard emulation or FPGA prototyping platforms (e.g., Synopsys ZeBu/HAPS, Cadence Palladium/Protium, Siemens Veloce).
• Experience in RTL design using Verilog or SystemVerilog.
• Experience writing scripts or developing automation workflows in Python, Perl, TCL, or Makefiles.

Preferred qualifications

• Experience scaling compilation and routing across multi-FPGA and enterprise emulation platforms.
• Experience verifying and troubleshooting complex semiconductor IP blocks.
• Experience collaborating with cross-functional design verification (DV) and silicon design teams.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google .

• Architect and drive advanced Register-Transfer Level (RTL) partitioning, Field-Programmable Gate Array (FPGA) synthesis, and validation strategies for industry-standard emulation platforms such as Synopsys ZeBu, Cadence Palladium, or Siemens Veloce.
• Define and execute comprehensive test suites, complex performance benchmarks, and software workloads to ensure pre-silicon verification and system-level validation.
• Guide advanced debugging methodologies to rapidly isolate and resolve complex functional failures within multi-million gate subsystem designs and full-chip environments.
• Lead initiatives to optimize model compile times, improve FPGA routing efficiency, and maximize hardware resource utilization across enterprise emulation farms.
• Architect custom automation workflows using modern scripting languages and collaborate with IP design and verification stakeholders to streamline continuous integration.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .