Senior FPGA Emulation & RTL Architect

Google; City of Poughkeepsie (NY); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is hiring for a role in which you will architect RTL partitioning, FPGA synthesis, and validation strategies across industry-standard emulation platforms. You will define comprehensive test suites and workloads for pre-silicon verification, guiding debugging to resolve complex failures in multi-million gate designs.

Your work will optimize compile times, routing efficiency, and hardware resource utilization across enterprise emulation farms while coordinating automation workflows with IP

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with industry-standard emulation or FPGA prototyping platforms (e.g., ZeBu/HAPS, Palladium/Protium, Veloce).
• Experience in RTL design using Verilog or SystemVerilog.
• Experience writing scripts or developing automation workflows in Python, Perl, TCL, or Makefiles.

Responsibilities

• Architect RTL partitioning and FPGA synthesis for emulation platforms.
• Define test suites, benchmarks, and workloads for pre-silicon verification.
• Lead debugging to resolve complex multi-million gate design issues.
• Optimize model compile times and FPGA routing across emulation farms.
• Architect automation workflows and collaborate with IP/design teams.

Skills

RTL design

Verilog/SystemVerilog

Python scripting

Automation workflows

Education

Bachelor's degree in EE/CE/CS

Tools

Synopsys ZeBu

Cadence Palladium/Protium

Siemens Veloce

Job description

Google is hiring for a role in which you will architect RTL partitioning, FPGA synthesis, and validation strategies across industry-standard emulation platforms. You will define comprehensive test suites and workloads for pre-silicon verification, guiding debugging to resolve complex failures in multi-million gate designs.

Your work will optimize compile times, routing efficiency, and hardware resource utilization across enterprise emulation farms while coordinating automation workflows with IP