Senior CPU Emulation Engineer - FPGA & RTL Automation

Google; Portland (OR); On-site; USD 163,000 - 236,000; Full time

Job summary

Google in Portland, OR is seeking a senior RTL/FPGA engineer to advance emulation and pre-silicon verification on industry-standard platforms. You will architect RTL, drive complex DV efforts, and improve FPGA synthesis, routing, and model compilation across multi-FPGA farms.

Ideal candidates bring 8+ years of experience, strong Verilog/SystemVerilog skills, and proficiency with scripting for automation. Competitive compensation includes equity and a 15% bonus target.

Qualifications

• Bachelor's degree or equivalent experience in EE/CS.
• 8 years of experience with emulation or FPGA platforms.
• RTL design with Verilog/SystemVerilog.
• Scripting in Python, Perl, TCL, or Makefiles.

Responsibilities

• Architect RTL partitioning and FPGA synthesis for emulation platforms.
• Define test suites and benchmarks for pre-silicon verification.
• Lead debugging to isolate functional failures in large designs.
• Optimize model compile times and FPGA routing in emulation farms.
• Create automation workflows and collaborate with IP teams.

Skills

RTL design

Verilog

SystemVerilog

FPGA prototyping

Python scripting

automation workflows

Education

Bachelor's degree

Tools

ZeBu

Palladium

Veloce

Job description

Google in Portland, OR is seeking a senior RTL/FPGA engineer to advance emulation and pre-silicon verification on industry-standard platforms. You will architect RTL, drive complex DV efforts, and improve FPGA synthesis, routing, and model compilation across multi-FPGA farms.

Ideal candidates bring 8+ years of experience, strong Verilog/SystemVerilog skills, and proficiency with scripting for automation. Competitive compensation includes equity and a 15% bonus target.