CPU Design Timing Engineer

Apple Inc.; United States; On-site; USD 160,000 - 190,000; Full time

Job summary

Apple Inc. is seeking a CPU Design Timing Engineer to close timing for high‑speed CPU designs in the Silicon Engineering Group. You will partner with CAD teams to create timing flows and scripts that streamline analysis, enabling faster cycles and higher yield.

The role requires deep collaboration with CPU micro‑architects and implementation engineers to ensure robust timing closure. The ideal candidate has extensive hands‑on experience with timing for GHz+ designs, cross‑domain timing, and

Qualifications

• BS degree in Electrical Engineering, Computer Science or related field.
• 10+ years of relevant industry experience.
• Experience with timing for 1 GHz+ designs and multiple clock/power domains.
• Familiarity with static timing tools and derate methodology.

Responsibilities

• Own timing closure of the CPU project in collaboration with the CAD team.
• Develop timing flows and scripts to improve analysis efficiency.
• Collaborate with CPU micro-architects and implementation engineers to drive timing closure.

Skills

Timing analysis

Scripting language proficiency

CPU design experience

Education

BS in Electrical Engineering or Computer Science

Tools

Primetime

Tempus

TCL

Perl

Python

Job description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!Apple’s Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.

Description

As a CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include but are not limited to:

• Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency
• Working extensively with CPU micro-architects and implementation engineers to drive timing closure for the CPU

Minimum Qualifications

• Minimum BS and 10+ years of relevant industry experience
• Experience working on timing for 1 ghz+ designs, including how to handle multiple clock and power domains
• Experience with one of the following static timing tools: Primetime or Tempus
• Experience with cross talk, noise, OCV, uncertainty, and derate methodology
• Experience with script writing and debugging in one or more of the following languages: TCL, Perl, Python

Preferred Qualifications

• Implementation experience on high performance CPU designs
• Working knowledge of CPU microarchitecture including common critical loops for timing and understanding of low power microarchitecture and implementation techniques for CPUs
• Good understanding of physical design tools and methodology including but not limited to physically aware synthesis and place & route tools and flows, extraction, and other analysis flows, and physical design verification (LEC, DVS, etc.)
• Knowledge of static timing tools and flows including how to handle multiple clock and power domains
• Knowledge of device physics especially aspects which impact timing: cross talk, noise, OCV, uncertainty and derate methodology

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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Apple accepts applications to this posting on an ongoing basis.