Contract Hardware Engineer Mid- #26-26416

Us Tech Solutions; San Jose (CA); Vor Ort; USD 180.000 - 240.000; Vollzeit

Zusammenfassung

Us Tech Solutions is seeking a diligent Design/SDC Engineer to own and optimize timing constraints across fullchip and block levels, collaborating with Front-end and Back-end teams for seamless physical design closure.

You will contribute to developing next-generation networking chips, leading timing analysis, scripting automation, and mentoring RTL owners on SDC development.

Qualifikationen

• Experience with block/full chip SDC development in functional and test modes.
• Strong background in Static Timing Analysis and industry STA tools.
• Proficiency in Verilog/SystemVerilog and ASIC design concepts.

Aufgaben

• Close fullchip SDCs with physical design and DFT teams across timing modes.
• Option to perform block level RTL design or IP integration.
• Develop methodology to promote block SDCs to fullchip and revert changes.
• Ensure SDC correctness early in the design cycle.
• Review block level SDCs and clock diagrams; mentor RTL owners.
• Create fullchip clocking diagrams and documentation.

Kenntnisse

SDC development

Static Timing Analysis

Clocking concepts

Verilog/SystemVerilog

Synthesis tools

Constraint tools

Formal Verification

Scripting (Python/ Perl/ TCL)

Ausbildung

Bachelor’s Degree in Electrical or Computer Engineering

Master’s Degree in Electrical or Computer Engineering

Tools

PrimeTime/Tempus

Synopsys DC/DCG/FC

Conformal Constraint Designer (CCD)

Spyglass

Synopsys Formality

Cadence LEC

Jobbeschreibung

Duration & Schedule

Duration: 11 months

Schedule: Day-1 Onsite

Job Description

• You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity.
• Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels.
• You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure.
• As part of this team, you’ll contribute to developing next-generation networking chips.

Responsibilities

• Being a member of the design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
• Option to also do block level RTL design or block or top-level IP integration.
• Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
• Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
• Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
• Creating fullchip clocking diagrams and related documentation.

Experience

• 8 Years of experience

Skillsets

• Experience with block/full chip SDC development in functional and test modes.
• Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus.
• Understanding of related digital design concepts (e.g., clocking and async boundaries).
• Experience with synthesis tools (e.g., Synopsys DC/DCG/FC), Verilog/System Verilog programming.
• Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence).
• Experience with Spyglass CDC and glitch analysis.
• Experience using Formal Verification: Synopsys Formality and Cadence LEC.
• Experience with scripting languages such as Python, Perl, or TCL.

Education

• Bachelor’s Degree in Electrical or Computer Engineering with 7 years of ASIC or related experience or Master’s Degree in Electrical or Computer Engineering with 5 years of ASIC or related experience.

Equal Opportunity Employer

US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.