Principal High Speed Mixed Signal Circuit Design Engineer

NOKIA; San Jose (CA); Presencial; USD 140.000 - 210.000; Jornada completa

Descripción de la vacante

Nokia in San Jose seeks a Principal Design Engineer to design and analyze high-speed analog/mixed-signal circuits, including data converters, PLLs, and SERDES, in advanced CMOS FinFET technologies. You will bring the design to production, creating technical differentiation that helps Nokia maintain market leadership.

Responsibilities include designing ADCs and DACs, creating layout floorplans, and evaluating trade-offs for power, area, and performance.

Formación

• Expertise in designing complex analog/mixed-signal IPs or chips in deep sub-micron CMOS tech.
• Experience bringing high-performance analog IPs to production (ADC/DAC and high-frequency PLL).
• Solid CMOS analog/mixed-signal methodology knowledge; layout effects awareness.

Responsabilidades

• Design, implement, simulate high-speed analog circuits (ADC/DAC).
• Create layout floorplans; supervise layout and guide layout engineers. Hands-on as needed.
• Evaluate topologies for power, area, bandwidth; develop analog testing plans with cross-functional teams.
• Support design methodologies and release flows.

Conocimientos

CAD tools proficiency

Verilog-A/Verilog-AMS

Educación

MS in EE or PhD in EE

Herramientas

Cadence Virtuoso

Spectre

Incisive

Calibre

EMX

TOTEM EM/IR

Descripción del empleo

The successful candidate shall possess the capability to design and analyze high‑speed, high‑performance analog/mixed‑signal circuits, including data converters, PLLs, and SERDES, in advanced CMOS FinFET technologies. She or he shall bring the design to production, creating technical differentiation that allows Infinera to maintain market leadership and revolutionize efficient high‑speed transmission.

Responsibilities

• Design, implement, and simulate the functionality and performance of various high‑speed analog circuits, including the ADCs and DACs.
• Create layout floor plans to optimize overall performance; supervise layout activities and provide concise guidelines to layout engineers, and be hands‑on in drawing layout if necessary.
• Explore trade‑offs of different topologies and propose the best solution to meet or exceed requirements in terms of power, area, linearity, bandwidth, etc.
• Develop analog testing plans and work with PE/TE teams to characterize functionality and performance of the products to ensure quality.
• Support and comply with the team's design methodologies and release flows.

Mandatory Knowledge/Skills/Abilities

• Extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and TOTEM EM/IR.
• Proven track record of designing complex analog/mixed‑signal IPs or chips in deep sub‑micron CMOS technologies.
• Experience bringing high‑performance analog IPs to production, including high‑speed ADC, DAC, and high‑frequency low‑jitter PLL.
• Decent understanding of CMOS analog/mixed‑signal design methodologies and circuit analysis.
• Good understanding of device physics and the impact of layout effects.
• Ability to perform behavioral modeling of blocks and circuits with Verilog‑A or Verilog‑AMS.
• Collaborative with other local or remote team members in a fast‑paced professional environment.

Preferred Knowledge/Skill/Abilities

• Fluent in verbal and written communications.
• Independent problem solver who conquers design challenges.
• Self‑motivated and detail‑oriented.
• Knowledge of (optical) communication theories and MATLAB coding.

Education and Experience Requirements

• Principal Design Engineer: M.S. in EE with 12+ years’ experience, or Ph.D. in EE with 8+ years’ experience.

Equal Opportunity Employer

Nokia is committed to inclusion and is an equal opportunity employer. Nokia’s employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.