Senior High-Speed Analog IC Design Engineer

NOKIA; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Nokia in San Jose seeks a Principal Design Engineer to design and analyze high-speed analog/mixed-signal circuits, including data converters, PLLs, and SERDES, in advanced CMOS FinFET technologies. You will bring the design to production, creating technical differentiation that helps Nokia maintain market leadership.

Responsibilities include designing ADCs and DACs, creating layout floorplans, and evaluating trade-offs for power, area, and performance.

Qualifications

• Expertise in designing complex analog/mixed-signal IPs or chips in deep sub-micron CMOS tech.
• Experience bringing high-performance analog IPs to production (ADC/DAC and high-frequency PLL).
• Solid CMOS analog/mixed-signal methodology knowledge; layout effects awareness.

Responsibilities

• Design, implement, simulate high-speed analog circuits (ADC/DAC).
• Create layout floorplans; supervise layout and guide layout engineers. Hands-on as needed.
• Evaluate topologies for power, area, bandwidth; develop analog testing plans with cross-functional teams.
• Support design methodologies and release flows.

Skills

CAD tools proficiency

Verilog-A/Verilog-AMS

Education

MS in EE or PhD in EE

Tools

Cadence Virtuoso

Spectre

Incisive

Calibre

EMX

TOTEM EM/IR

Job description

Nokia in San Jose seeks a Principal Design Engineer to design and analyze high-speed analog/mixed-signal circuits, including data converters, PLLs, and SERDES, in advanced CMOS FinFET technologies. You will bring the design to production, creating technical differentiation that helps Nokia maintain market leadership.

Responsibilities include designing ADCs and DACs, creating layout floorplans, and evaluating trade-offs for power, area, and performance.